[U-Boot] [U-Boot, U-boot, v3, 3/4] keystone2: ecc: add ddr3 error detection and correction support

[Tom Rini]

On Wed, Oct 22, 2014 at 05:47:58PM +0300, Khoronzhuk, Ivan wrote:

> From: Vitaly Andrianov <vitalya at ti.com>
> 
> This patch adds the DDR3 ECC support to enable ECC in the DDR3
> EMIF controller for Keystone II devices.
> 
> By default, ECC will only be enabled if RMW is supported in the
> DDR EMIF controller. The entire DDR memory will be scrubbed to
> zero using an EDMA channel after ECC is enabled and before
> u-boot is re-located to DDR memory.
> 
> An ecc_test environment variable is added for ECC testing.
> If ecc_test is set to 0, a detection of 2-bit error will reset
> the device, if ecc_test is set to 1, 2-bit error detection
> will not reset the device, user can still boot the kernel to
> check the ECC error handling in kernel.
> 
> Signed-off-by: Hao Zhang <hzhang at ti.com>
> Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk at ti.com>

Applied to u-boot-ti/master, thanks!

-- 
Tom
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