[U-Boot] [PATCH v3 4/4] arm: interrupt_init: set sp in IRQ/FIQ modes

[Albert ARIBAUD]

Hello Georges,

On Sun, 26 Oct 2014 23:25:26 +0100, Georges Savoundararadj
<savoundg at gmail.com> wrote:
> Before this commit, the stack addresses for IRQ and FIQ modes,
> IRQ_STACK_START and FIQ_STACK_START, were computed in interrupt_init
> but they were not used.
> 
> This commit sets the stack pointers for IRQ and FIQ modes.
> 
> Signed-off-by: Georges Savoundararadj <savoundg at gmail.com>
> Cc: Albert Aribaud <albert.u.boot at aribaud.net>
> 
> ---
> 
> Changes in v3:
> - None
> 
> Changes in v2:
> - Reword the commit message
> 
>  arch/arm/lib/interrupts.c | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
> 
> diff --git a/arch/arm/lib/interrupts.c b/arch/arm/lib/interrupts.c
> index f6b7c03..49c1bf3 100644
> --- a/arch/arm/lib/interrupts.c
> +++ b/arch/arm/lib/interrupts.c
> @@ -34,6 +34,25 @@ int interrupt_init (void)
>  	IRQ_STACK_START_IN = gd->irq_sp + 8;
>  	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
>  
> +	__asm__ __volatile__("msr cpsr_c, %0\n"
> +			     "mov sp, %1\n"
> +			     :
> +			     : "r" (IRQ_MODE | I_BIT | F_BIT),
> +			       "r" (IRQ_STACK_START)
> +			     : "memory");
> +
> +	__asm__ __volatile__("msr cpsr_c, %0\n"
> +			     "mov sp, %1\n"
> +			     :
> +			     : "r" (FIQ_MODE | I_BIT | F_BIT),
> +			       "r" (FIQ_STACK_START)
> +			     : "memory");
> +
> +	__asm__ __volatile__("msr cpsr_c, %0"
> +			     :
> +			     : "r" (SVC_MODE | I_BIT | F_BIT)
> +			     : "memory");

This sequence is trashing bits in CPSR which are unrelated to its
goal, including reserved bits which, as per ARM documentation, are to
be preserved. The sequence should initial CPSR and only change the
mode, I and F bits.

>  	return arch_interrupt_init();
>  }
>  
> -- 
> 2.1.2

Amicalement,
-- 
Albert.