[U-Boot] [v3 PATCH 11/12] arm, at91, spl: add spl support for the taurus board
Heiko Schocher
hs at denx.de
Fri Oct 31 08:31:05 CET 2014
replaces the at91bootstrap code with SPL code.
make the spl image with:
./tools/mkimage -T atmelimage -d spl/u-boot-spl.bin spl/boot.bin
this writes the length of the spl image into the 6th
execption vector. This is needed from the ROM bootloader.
Signed-off-by: Heiko Schocher <hs at denx.de>
Reviewed-by: Bo Shen <voice.shen at atmel.com>
---
Changes in v3:
add comment from Bo Shen:
- make matrix_init weak, and add it in taurs board code
- add Reviewed-by from Bo Shen
Changes in v2:
- rename function "nand_erase_one" to "spl_nand_erase_one" as
Scott Wood suggested
arch/arm/Kconfig | 1 +
board/siemens/taurus/taurus.c | 82 +++++++++++++++++++++++++++++++++++++------
configs/taurus_defconfig | 5 +--
include/configs/taurus.h | 52 ++++++++++++++++++++++++++-
4 files changed, 127 insertions(+), 13 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 171ad03..ab45703 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -210,6 +210,7 @@ config TARGET_CORVUS
select CPU_ARM926EJS
config TARGET_TAURUS
+ select SUPPORT_SPL
bool "Support taurus"
select CPU_ARM926EJS
diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c
index 76609c7..b8ff478 100644
--- a/board/siemens/taurus/taurus.c
+++ b/board/siemens/taurus/taurus.c
@@ -21,6 +21,8 @@
#include <asm/arch/at91_rstc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/at91sam9_sdramc.h>
+#include <asm/arch/clk.h>
+#include <linux/mtd/nand.h>
#include <atmel_mci.h>
#include <asm/arch/at91_spi.h>
#include <spi.h>
@@ -30,7 +32,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_CMD_NAND
static void taurus_nand_hw_init(void)
{
struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
@@ -63,15 +64,77 @@ static void taurus_nand_hw_init(void)
/* Enable NandFlash */
at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
+
+#if defined(CONFIG_SPL_BUILD)
+#include <spl.h>
+#include <nand.h>
+
+void matrix_init(void)
+{
+ struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+
+ writel((readl(&mat->scfg[3]) & (~AT91_MATRIX_SLOT_CYCLE))
+ | AT91_MATRIX_SLOT_CYCLE_(0x40),
+ &mat->scfg[3]);
+}
+
+void at91_spl_board_init(void)
+{
+ taurus_nand_hw_init();
+
+ /* Configure recovery button PINs */
+ at91_set_gpio_input(AT91_PIN_PA31, 1);
+
+ /* check if button is pressed */
+ if (at91_get_gpio_value(AT91_PIN_PA31) == 0) {
+ u32 boot_device;
+
+ debug("Recovery button pressed\n");
+ boot_device = spl_boot_device();
+ switch (boot_device) {
+#ifdef CONFIG_SPL_NAND_SUPPORT
+ case BOOT_DEVICE_NAND:
+ nand_init();
+ spl_nand_erase_one(0, 0);
+ break;
+#endif
+ }
+ }
+}
+
+void mem_init(void)
+{
+ struct at91_matrix *ma = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ struct sdramc_reg setting;
+
+ at91_sdram_hw_init();
+ setting.cr = (AT91_SDRAMC_NC_9 |
+ AT91_SDRAMC_NR_13 |
+ AT91_SDRAMC_CAS_3 |
+ AT91_SDRAMC_NB_4 |
+ AT91_SDRAMC_DBW_32 |
+ AT91_SDRAMC_TWR_VAL(3) |
+ AT91_SDRAMC_TRC_VAL(9) |
+ AT91_SDRAMC_TRP_VAL(3) |
+ AT91_SDRAMC_TRCD_VAL(3) |
+ AT91_SDRAMC_TRAS_VAL(6) |
+ AT91_SDRAMC_TXSR_VAL(10));
+ setting.mdr = AT91_SDRAMC_MD_SDRAM;
+ setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000;
+
+
+ writel(readl(&ma->ebicsa) | AT91_MATRIX_CS1A_SDRAMC |
+ AT91_MATRIX_VDDIOMSEL_3_3V | AT91_MATRIX_EBI_IOSR_SEL,
+ &ma->ebicsa);
+ sdramc_initialize(ATMEL_BASE_CS1, &setting);
+}
#endif
#ifdef CONFIG_MACB
static void taurus_macb_hw_init(void)
{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
/* Enable EMAC clock */
- writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
+ at91_periph_clk_enable(ATMEL_ID_EMAC0);
/*
* Disable pull-up on:
@@ -119,12 +182,12 @@ int board_mmc_init(bd_t *bd)
int board_early_init_f(void)
{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
/* Enable clocks for all PIOs */
- writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
- (1 << ATMEL_ID_PIOC),
- &pmc->pcer);
+ at91_periph_clk_enable(ATMEL_ID_PIOA);
+ at91_periph_clk_enable(ATMEL_ID_PIOB);
+ at91_periph_clk_enable(ATMEL_ID_PIOC);
+
+ at91_seriald_hw_init();
return 0;
}
@@ -149,7 +212,6 @@ int board_init(void)
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
- at91_seriald_hw_init();
#ifdef CONFIG_CMD_NAND
taurus_nand_hw_init();
#endif
diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig
index 9870048..438e25d 100644
--- a/configs/taurus_defconfig
+++ b/configs/taurus_defconfig
@@ -1,3 +1,4 @@
+CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2067,BOARD_TAURUS"
-CONFIG_ARM=y
-CONFIG_TARGET_TAURUS=y
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_TAURUS=y
diff --git a/include/configs/taurus.h b/include/configs/taurus.h
index ba9496f..20194ae 100644
--- a/include/configs/taurus.h
+++ b/include/configs/taurus.h
@@ -34,7 +34,7 @@
*/
-#define CONFIG_SYS_TEXT_BASE 0x23f00000
+#define CONFIG_SYS_TEXT_BASE 0x21000000
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
@@ -168,4 +168,54 @@
#define CONFIG_SYS_MALLOC_LEN \
ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
+/* Defines for SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE 0x0
+#define CONFIG_SPL_MAX_SIZE (11 * 1024)
+#define CONFIG_SPL_STACK (16 * 1024)
+
+#define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE
+#define CONFIG_SPL_BSS_MAX_SIZE (3 * 1024)
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14)
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SYS_USE_NANDFLASH 1
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_NAND_RAW_ONLY
+#define CONFIG_SPL_NAND_SOFTECC
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+
+#define CONFIG_SYS_NAND_SIZE (256*1024*1024)
+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
+#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
+ CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCSIZE 256
+#define CONFIG_SYS_NAND_ECCBYTES 3
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
+ 48, 49, 50, 51, 52, 53, 54, 55, \
+ 56, 57, 58, 59, 60, 61, 62, 63, }
+
+
+#define CONFIG_SPL_ATMEL_SIZE
+#define CONFIG_SYS_MASTER_CLOCK 132096000
+#define AT91_PLL_LOCK_TIMEOUT 1000000
+#define CONFIG_SYS_AT91_PLLA 0x202A3F01
+#define CONFIG_SYS_MCKR 0x1300
+#define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR)
+#define CONFIG_SYS_AT91_PLLB 0x10193F05
#endif
--
1.8.3.1
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