[U-Boot] [PATCH v2] imx: ddr: Move mx6q_4x_mt41j128.cfg to mx6sabresd board dir

[Eric Nelson]

Hi Fabio,

On 09/01/2014 03:27 PM, Fabio Estevam wrote:
> Hi Wolfgang,
> 
> On Mon, Sep 1, 2014 at 4:24 PM, Wolfgang Denk <wd at denx.de> wrote:
>> Dear Nitin Garg,
>>
>> In message <1409581243-12695-1-git-send-email-nitin.garg at freescale.com> you wrote:
>>> Move board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg to
>>> board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg as this is
>>> was designed for the mx6sabresd board. This also updates the
>>> cgtqmx6qeval which makes use of this configuration.
>>
>> I've made my mind up.  I hereby NAK this patch, as it would basically
>> revert Fabio Estevam's commit af7ec0b which moved the originally
>> board-specific code to a common place:
>>
>>         commit af7ec0b0582f658873713c311497626c571f3b31
>>         Author: Fabio Estevam <fabio.estevam at freescale.com>
>>         Date:   Thu Sep 13 03:18:19 2012 +0000
>>
>>         mx6q: Factor out common DDR3 init code
>>
>>         Factor out common DDR3 initialization code, allowing easier
>>         maintainance of such scripts.
>>
>>         Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
>>
>> Fabio's intention was a good one, as is proven by the re-use of this
>> code by other boards.
> 
> Let me provide some background on the reason I sent that patch: at
> that time we had the same DDR3 init code for several boards, such as
> mx6qsabresd, nitrogen, sabrelite, so I wanted to avoid duplicating the
> same init for several boards.
> 

Specifically, the Nitrogen and SABRE Lite designs use a different
memory layout from SABRE SD and SABRE Auto and the DDR calibration
data is quite different.

Boards may share the same memory arrangement, but it's unlikely
that the calibration process has been performed on multiple board
types and achieved the same values.

It's possible that many boards copied the layout and stack-up
from the SABRE SD design such that the board functions properly
with the SABRE SD values, but also likely that some vendors just
don't know that their calibration results will differ.

> After sometime, each board used to followed its own specific settings,
> as the DDR3 init is very dependant on board layout and some
> optimizations that are valid for one board does not apply to others.
> Each board developer has to be really careful about properly
> configuring DDR in order to achieve stability, so re-use of the DCD
> settings should be done really carefully.
> 

Note that mx6q_4x_mt41j128.cfg combines multiple things in the
same config file.

Separating them (especially the calibration data) as done in
the nitrogen6x/ tree will help distinguish between the design-time
parts of the configuration and the measured calibration.

> As it stands today only mx6qsabresd and congatec share the same script.
> 

I believe that the Wand board is using the configuration files
from the nitrogen6x tree.

> I think Nitin's patch goes in the right direction, as it makes clearer
> for other developers that the DDR specific settings are optmized for
> mx6qsabresd only. Of course people can re-use it, like congatec board
> does today, but if in the future we find some more optimal settings
> for this board we should apply it to mx6sabresd, but we really don't
> know the consequences into other hardware. So they have been warned
> :-)
> 
> Moving forward we should really get rid of this DCD syntax and move to
> SPL style.
> 

There's no way to completely get rid of the DCD. It may be possible
(even beneficial) to do run-time DDR calibration, but that's off-topic
in this thread.

Regards,


Eric