[U-Boot] [PATCH v6 05/17] ls102xa: etsec: Add etsec support for LS102xA

[Alison Wang]

This patch is to add etsec support for LS102xA. First, Little-endian
descriptor mode should be enabled. So RxBDs and TxBDs are interpreted
with little-endian byte ordering. Second, TSEC_SIZE and TSEC_MDIO_OFFSET
are different from PowerPC, redefine them for LS1021xA.

Signed-off-by: Alison Wang <alison.wang at freescale.com>
---
Change log:
 v6: Fix checkpatch error.
     Make the commit more clear.
 v5: No change.
 v4: No change.
 v3: No change.
 v2: Add private mdio read and write support.

 drivers/net/tsec.c | 7 +++++++
 include/tsec.h     | 7 ++++++-
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index e9138f0..79d6561 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -20,6 +20,7 @@
 #include <fsl_mdio.h>
 #include <asm/errno.h>
 #include <asm/processor.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -270,6 +271,9 @@ void redundant_init(struct eth_device *dev)
 	out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
 	out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
 	clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
+#ifdef CONFIG_LS102XA
+	setbits_be32(&regs->dmactrl, DMACTRL_LE);
+#endif
 
 	do {
 		uint16_t status;
@@ -366,6 +370,9 @@ static void startup_tsec(struct eth_device *dev)
 	out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
 	out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
 	clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
+#ifdef CONFIG_LS102XA
+	setbits_be32(&regs->dmactrl, DMACTRL_LE);
+#endif
 }
 
 /* This returns the status bits of the device.	The return value
diff --git a/include/tsec.h b/include/tsec.h
index 2054715..1119d2c 100644
--- a/include/tsec.h
+++ b/include/tsec.h
@@ -20,10 +20,14 @@
 #include <net.h>
 #include <config.h>
 #include <phy.h>
-#include <fsl_mdio.h>
 
+#ifdef CONFIG_LS102XA
+#define TSEC_SIZE		0x40000
+#define TSEC_MDIO_OFFSET	0x40000
+#else
 #define TSEC_SIZE 		0x01000
 #define TSEC_MDIO_OFFSET	0x01000
+#endif
 
 #define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + 0x520)
 
@@ -128,6 +132,7 @@
 #define DMACTRL_INIT_SETTINGS	0x000000c3
 #define DMACTRL_GRS		0x00000010
 #define DMACTRL_GTS		0x00000008
+#define DMACTRL_LE		0x00008000
 
 #define TSTAT_CLEAR_THALT	0x80000000
 #define RSTAT_CLEAR_RHALT	0x00800000
-- 
2.1.0.27.g96db324