[U-Boot] [PATCH 2/2] board/ls1021aqds_d4: Add DDR4 support
Otavio Salvador
otavio at ossystems.com.br
Fri Sep 12 00:26:58 CEST 2014
On Thu, Sep 11, 2014 at 5:32 PM, York Sun <yorksun at freescale.com> wrote:
> LS1021AQDS has a variant with DDR4 slot. This patch adds a new target for
> this variant and enables DDR4 support. RAW timing parameters are not added
> for DDR4. The board timing parameters are only tuned for single-rank 1600
> and 1800MT/s with Micron DIMM 9ASF51272AZ-2G1A1 due to availability.
>
> Signed-off-by: York Sun <yorksun at freescale.com>
> ---
> arch/arm/Kconfig | 3 +++
> arch/arm/include/asm/arch-ls102xa/config.h | 5 +++++
> board/freescale/ls1021aqds/Kconfig | 2 +-
> board/freescale/ls1021aqds/ddr.c | 9 ++++++++-
> board/freescale/ls1021aqds/ddr.h | 10 ++++++++++
> ...s_nor_defconfig => ls1021aqds_d4_nor_defconfig} | 1 +
> include/configs/ls1021aqds.h | 4 +++-
> 7 files changed, 31 insertions(+), 3 deletions(-)
> copy configs/{ls1021aqds_nor_defconfig => ls1021aqds_d4_nor_defconfig} (50%)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 11143a8..49c4b5a 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -473,6 +473,9 @@ config TARGET_LS2085A_SIMU
> config TARGET_LS1021AQDS
> bool "Support ls1021aqds_nor"
>
> +config TARGET_LS1021AQDS_D4
> + bool "Support ls1021aqds_nor with DDR4"
Use _DDR4 for the target, easier to understand when reading later.
> config TARGET_LS1021ATWR
> bool "Support ls1021atwr_nor"
>
> diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
> index ed78c33..a500b5b 100644
> --- a/arch/arm/include/asm/arch-ls102xa/config.h
> +++ b/arch/arm/include/asm/arch-ls102xa/config.h
> @@ -50,7 +50,11 @@
> #ifdef CONFIG_DDR_SPD
> #define CONFIG_SYS_FSL_DDR_BE
> #define CONFIG_VERY_BIG_RAM
> +#ifdef CONFIG_SYS_FSL_DDR4
> +#define CONFIG_SYS_FSL_DDRC_GEN4
> +#else
> #define CONFIG_SYS_FSL_DDRC_ARM_GEN3
> +#endif
> #define CONFIG_SYS_FSL_DDR
> #define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
> #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
> @@ -71,6 +75,7 @@
> #define CONFIG_MAX_CPUS 2
> #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
> #define CONFIG_NUM_DDR_CONTROLLERS 1
> +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
> #else
> #error SoC not defined
> #endif
> diff --git a/board/freescale/ls1021aqds/Kconfig b/board/freescale/ls1021aqds/Kconfig
> index c28bd2b..1f60d95 100644
> --- a/board/freescale/ls1021aqds/Kconfig
> +++ b/board/freescale/ls1021aqds/Kconfig
> @@ -1,4 +1,4 @@
> -if TARGET_LS1021AQDS
> +if TARGET_LS1021AQDS || TARGET_LS1021AQDS_D4
Same here.
> config SYS_CPU
> string
> diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c
> index 679c654..5898e33 100644
> --- a/board/freescale/ls1021aqds/ddr.c
> +++ b/board/freescale/ls1021aqds/ddr.c
> @@ -79,7 +79,6 @@ found:
> */
> popts->wrlvl_override = 1;
> popts->wrlvl_sample = 0xf;
> - popts->cswl_override = DDR_CSWL_CS0;
>
> /*
> * Rtt and Rtt_WR override
> @@ -89,9 +88,17 @@ found:
> /* Enable ZQ calibration */
> popts->zq_en = 1;
>
> +#ifdef CONFIG_SYS_FSL_DDR4
> + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
> + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
> + DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
> +#else
> + popts->cswl_override = DDR_CSWL_CS0;
> +
> /* DHC_EN =1, ODT = 75 Ohm */
> popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
> popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
> +#endif
> }
>
> #ifdef CONFIG_SYS_DDR_RAW_TIMING
> diff --git a/board/freescale/ls1021aqds/ddr.h b/board/freescale/ls1021aqds/ddr.h
> index 16d87cb..f819c99 100644
> --- a/board/freescale/ls1021aqds/ddr.h
> +++ b/board/freescale/ls1021aqds/ddr.h
> @@ -30,6 +30,13 @@ static const struct board_specific_parameters udimm0[] = {
> * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
> * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
> */
> +#ifdef CONFIG_SYS_FSL_DDR4
> + {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
> + {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
> + {1, 1666, 0, 4, 8, 0x090A0B0B, 0x0C0D0E0C,},
> + {1, 1900, 0, 4, 9, 0x0A0B0C0B, 0x0D0E0F0D,},
> + {1, 2200, 0, 4, 10, 0x0B0C0D0C, 0x0E0F110E,},
> +#elif defined(CONFIG_SYS_FSL_DDR3)
> {1, 833, 1, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
> {1, 1350, 1, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
> {1, 833, 2, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
> @@ -39,6 +46,9 @@ static const struct board_specific_parameters udimm0[] = {
> {2, 1350, 0, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
> {2, 1666, 4, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
> {2, 1666, 0, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
> +#else
> +#error DDR type not defined
> +#endif
> {}
> };
>
> diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_d4_nor_defconfig
> similarity index 50%
> copy from configs/ls1021aqds_nor_defconfig
> copy to configs/ls1021aqds_d4_nor_defconfig
> index 9e42d61..3c57481 100644
> --- a/configs/ls1021aqds_nor_defconfig
> +++ b/configs/ls1021aqds_d4_nor_defconfig
> @@ -1,2 +1,3 @@
> +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
> CONFIG_ARM=y
> CONFIG_TARGET_LS1021AQDS=y
> diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
> index 657e3b6..bb47813 100644
> --- a/include/configs/ls1021aqds.h
> +++ b/include/configs/ls1021aqds.h
> @@ -49,10 +49,12 @@ unsigned long get_board_ddr_clk(void);
> #define CONFIG_DDR_SPD
> #define SPD_EEPROM_ADDRESS 0x51
> #define CONFIG_SYS_SPD_BUS_NUM 0
> -#define CONFIG_SYS_DDR_RAW_TIMING
>
> #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
> +#ifndef CONFIG_SYS_FSL_DDR4
> #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
> +#define CONFIG_SYS_DDR_RAW_TIMING
> +#endif
> #define CONFIG_DIMM_SLOTS_PER_CTLR 1
> #define CONFIG_CHIP_SELECTS_PER_CTRL 4
>
> --
> 1.7.9.5
>
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--
Otavio Salvador O.S. Systems
http://www.ossystems.com.br http://code.ossystems.com.br
Mobile: +55 (53) 9981-7854 Mobile: +1 (347) 903-9750
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