[U-Boot] [PATCH 07/10] sunxi: Fix end of kernel memory alignment for A33

[Mark Rutland]

On Thu, Apr 16, 2015 at 08:32:03AM +0100, Hans de Goede wrote:
> Hi,
> 
> On 15-04-15 21:57, Ian Campbell wrote:
> > On Tue, 2015-04-14 at 18:06 +0200, Hans de Goede wrote:
> >> For unknown reasons the A33 needs the end of the memory we report to the
> >> kernel to be aligned to a multiple of 4 MiB.
> >
> > Do you really mean "the A33 needs" (as in the processor itself) or do
> > you actually mean "the A33 kernel port"?
> >
> > If the latter than can't that be investigated/fixed instead of hacked
> > here? That would be far more preferable.
> 
> I mean the former, it seems that the SoC itself cannot handle dram
> ranges with different cache policies which are not aligned to 4 MiB,
> at least that is my WAG what is going on here.

That sounds incredibly suspicious.

What do you mean w.r.t. different cache policies -- what does that have
to do with the end of DRAM? What problem do you see?

It would be worth reporting this on lakml.

> I've been using an a23 dtb + generic multi-platform kernel for my testing
> (as said before the a33 really is almost the same design), and that boots
> fine without this alignment hack on an actual A23 device, so this is not
> a kernel limitation.

Not necessarily. Is RAM at the same location on both SoCs? What about
other devices and carevouts?

It could be htat the stars happen to align and we're finally caught out
by some dodgy maths.

Mark.