[U-Boot] [PATCH V5 6/6] imx: mx6qpsabreauto: Add MX6QP SABREAUTO CPU3 board support
Stefano Babic
sbabic at denx.de
Sun Aug 2 10:47:31 CEST 2015
On 11/07/2015 05:38, Peng Fan wrote:
> 1. Add DDR script for mx6qpsabreauto board.
> 2. On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9]
> and init the enet pll output to 125Mhz.
> 3. On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN.
>
> Build target: mx6qpsabreauto_config
>
> Boot Log:
> U-Boot 2015.07-rc2-00071-gfd985ff (Jun 29 2015 - 22:10:55 +0800)
>
> CPU: Freescale i.MX6QP rev1.0 996 MHz (running at 792 MHz)
> CPU: Automotive temperature grade (-40C to 125C) at 34C
> Reset cause: POR
> Board: MX6Q-Sabreauto revA
> I2C: ready
> DRAM: 2 GiB
> PMIC: PFUZE100 ID=0x10
> Flash: 32 MiB
> NAND: 0 MiB
> MMC: FSL_SDHC: 0
> *** Warning - bad CRC, using default environment
>
> No panel detected: default to HDMI
> Display: HDMI (1024x768)
> In: serial
> Out: serial
> Err: serial
> Net: FEC [PRIME]
> Hit any key to stop autoboot: 0
>
> Note:
> In this patch, we still add a new config mx6qpsabreauto_config,
> since SPL is not supported now, and IMX_CONFIG is needed at
> build time, so add this config. Future, when SPL is converted,
> this config can be removed.
>
> Signed-off-by: Peng Fan <Peng.Fan at freescale.com>
> Signed-off-by: Robin Gong <b38343 at freescale.com>
> Signed-off-by: Ye.Li <B37916 at freescale.com>
> Reviewed-by: Fabio Estevam <fabio.estevam at freescale.com>
> ---
>
> Changes v5:
> none
>
> Changes v4:
> Add Fabio's Reviewed-by
>
> Changes v3:
> 1. runtime setting DTB
> 2. In this patch, we still add a new config mx6qpsabreauto_config,
> since SPL is not supported now, and IMX_CONFIG is needed at
> build time, so add this config. All the patches in this patch set
> have been reworked with CONFIG_MX6QP removed to align
> with runtime check, but this IMX_CONFIG is needed at build time.
> Future, when SPL is converted, this config can be removed.
>
> Changes v2:
> 1. Remove unused macro in current upstream uboot.
> 2. setup_fec, remove non 6qp code. Add comments for gpr setting.
> 3. mx6qp.cfg is still same with v1. The settings is from IC and passed
> memory ddr stress test. Since we current have no plan to add SPL,
> so leave settings unchanged.
>
> board/freescale/mx6qsabreauto/mx6qp.cfg | 145 ++++++++++++++++++++++++++
> board/freescale/mx6qsabreauto/mx6qsabreauto.c | 33 ++++--
> configs/mx6qpsabreauto_defconfig | 4 +
> include/configs/mx6sabre_common.h | 2 +
> 4 files changed, 177 insertions(+), 7 deletions(-)
> create mode 100644 board/freescale/mx6qsabreauto/mx6qp.cfg
> create mode 100644 configs/mx6qpsabreauto_defconfig
>
> diff --git a/board/freescale/mx6qsabreauto/mx6qp.cfg b/board/freescale/mx6qsabreauto/mx6qp.cfg
> new file mode 100644
> index 0000000..2298c77
> --- /dev/null
> +++ b/board/freescale/mx6qsabreauto/mx6qp.cfg
> @@ -0,0 +1,145 @@
> +/*
> + * Copyright (C) 2015 Freescale Semiconductor, Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + *
> + * Refer doc/README.imximage for more details about how-to configure
> + * and create imximage boot image
> + *
> + * The syntax is taken as close as possible with the kwbimage
> + */
> +/* image version */
> +
> +#define __ASSEMBLY__
> +#include <config.h>
> +
> +IMAGE_VERSION 2
> +
> +/*
> + * Boot Device : one of spi, sd, eimnor, nand, sata:
> + * spinor: flash_offset: 0x0400
> + * nand: flash_offset: 0x0400
> + * sata: flash_offset: 0x0400
> + * sd/mmc: flash_offset: 0x0400
> + * eimnor: flash_offset: 0x1000
> + */
> +BOOT_FROM sd
> +
> +/*
> + * Device Configuration Data (DCD)
> + *
> + * Each entry must have the format:
> + * Addr-type Address Value
> + *
> + * where:
> + * Addr-type register length (1,2 or 4 bytes)
> + * Address absolute address of the register
> + * value value to be stored in the register
> + */
> +DATA 4 0x020e0798 0x000C0000
> +DATA 4 0x020e0758 0x00000000
> +DATA 4 0x020e0588 0x00000030
> +DATA 4 0x020e0594 0x00000030
> +DATA 4 0x020e056c 0x00000030
> +DATA 4 0x020e0578 0x00000030
> +DATA 4 0x020e074c 0x00000030
> +DATA 4 0x020e057c 0x00000030
> +DATA 4 0x020e058c 0x00000000
> +DATA 4 0x020e059c 0x00000030
> +DATA 4 0x020e05a0 0x00000030
> +DATA 4 0x020e078c 0x00000030
> +DATA 4 0x020e0750 0x00020000
> +DATA 4 0x020e05a8 0x00000030
> +DATA 4 0x020e05b0 0x00000030
> +DATA 4 0x020e0524 0x00000030
> +DATA 4 0x020e051c 0x00000030
> +DATA 4 0x020e0518 0x00000030
> +DATA 4 0x020e050c 0x00000030
> +DATA 4 0x020e05b8 0x00000030
> +DATA 4 0x020e05c0 0x00000030
> +DATA 4 0x020e0774 0x00020000
> +DATA 4 0x020e0784 0x00000030
> +DATA 4 0x020e0788 0x00000030
> +DATA 4 0x020e0794 0x00000030
> +DATA 4 0x020e079c 0x00000030
> +DATA 4 0x020e07a0 0x00000030
> +DATA 4 0x020e07a4 0x00000030
> +DATA 4 0x020e07a8 0x00000030
> +DATA 4 0x020e0748 0x00000030
> +DATA 4 0x020e05ac 0x00000030
> +DATA 4 0x020e05b4 0x00000030
> +DATA 4 0x020e0528 0x00000030
> +DATA 4 0x020e0520 0x00000030
> +DATA 4 0x020e0514 0x00000030
> +DATA 4 0x020e0510 0x00000030
> +DATA 4 0x020e05bc 0x00000030
> +DATA 4 0x020e05c4 0x00000030
> +DATA 4 0x021b0800 0xa1390003
> +DATA 4 0x021b080c 0x001b001e
> +DATA 4 0x021b0810 0x002e0029
> +DATA 4 0x021b480c 0x001b002a
> +DATA 4 0x021b4810 0x0019002c
> +DATA 4 0x021b083c 0x43240334
> +DATA 4 0x021b0840 0x0324031a
> +DATA 4 0x021b483c 0x43340344
> +DATA 4 0x021b4840 0x03280276
> +DATA 4 0x021b0848 0x44383A3E
> +DATA 4 0x021b4848 0x3C3C3846
> +DATA 4 0x021b0850 0x2e303230
> +DATA 4 0x021b4850 0x38283E34
> +DATA 4 0x021b081c 0x33333333
> +DATA 4 0x021b0820 0x33333333
> +DATA 4 0x021b0824 0x33333333
> +DATA 4 0x021b0828 0x33333333
> +DATA 4 0x021b481c 0x33333333
> +DATA 4 0x021b4820 0x33333333
> +DATA 4 0x021b4824 0x33333333
> +DATA 4 0x021b4828 0x33333333
> +DATA 4 0x021b08c0 0x24912492
> +DATA 4 0x021b48c0 0x24912492
> +DATA 4 0x021b08b8 0x00000800
> +DATA 4 0x021b48b8 0x00000800
> +DATA 4 0x021b0004 0x00020036
> +DATA 4 0x021b0008 0x09444040
> +DATA 4 0x021b000c 0x898E7955
> +DATA 4 0x021b0010 0xFF328F64
> +DATA 4 0x021b0014 0x01FF00DB
> +DATA 4 0x021b0018 0x00001740
> +DATA 4 0x021b001c 0x00008000
> +
> +DATA 4 0x021b002c 0x000026d2
> +DATA 4 0x021b0030 0x008E1023
> +DATA 4 0x021b0040 0x00000047
> +DATA 4 0x021b0400 0x14420000
> +DATA 4 0x021b0000 0x841A0000
> +DATA 4 0x00bb0008 0x00000004
> +DATA 4 0x00bb000c 0x2891E41A
> +DATA 4 0x00bb0038 0x00000564
> +DATA 4 0x00bb0014 0x00000040
> +DATA 4 0x00bb0028 0x00000020
> +DATA 4 0x00bb002c 0x00000020
> +DATA 4 0x021b001c 0x04088032
> +DATA 4 0x021b001c 0x00008033
> +DATA 4 0x021b001c 0x00048031
> +DATA 4 0x021b001c 0x09408030
> +DATA 4 0x021b001c 0x04008040
> +DATA 4 0x021b0020 0x00005800
> +DATA 4 0x021b0818 0x00011117
> +DATA 4 0x021b4818 0x00011117
> +DATA 4 0x021b0004 0x00025576
> +DATA 4 0x021b0404 0x00011006
> +DATA 4 0x021b001c 0x00000000
> +/* set the default clock gate to save power */
> +DATA 4, 0x020c4068, 0x00C03F3F
> +DATA 4, 0x020c406c, 0x0030FC03
> +DATA 4, 0x020c4070, 0x0FFFC000
> +DATA 4, 0x020c4074, 0x3FF00000
> +DATA 4, 0x020c4078, 0xFFFFF300
> +DATA 4, 0x020c407c, 0x0F0000F3
> +DATA 4, 0x020c4080, 0x00000FFF
> +
> +/* enable AXI cache for VDOA/VPU/IPU */
> +DATA 4, 0x020e0010, 0xF00000CF
> +/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
> +DATA 4, 0x020e0018, 0x77177717
> +DATA 4, 0x020e001c, 0x77177717
> diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
> index 943a4bd..98602f8 100644
> --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
> +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
> @@ -354,9 +354,22 @@ int board_phy_config(struct phy_device *phydev)
> return 0;
> }
>
> -int board_eth_init(bd_t *bis)
> +static void setup_fec(void)
> {
> + if (is_mx6dqp()) {
> + /*
> + * select ENET MAC0 TX clock from PLL
> + */
> + imx_iomux_set_gpr_register(5, 9, 1, 1);
> + enable_fec_anatop_clock(ENET_125MHZ);
> + }
> +
> setup_iomux_enet();
> +}
> +
> +int board_eth_init(bd_t *bis)
> +{
> + setup_fec();
>
> return cpu_eth_init(bis);
> }
> @@ -495,17 +508,21 @@ int board_spi_cs_gpio(unsigned bus, unsigned cs)
> int power_init_board(void)
> {
> struct pmic *p;
> - unsigned int ret;
> + unsigned int value;
>
> p = pfuze_common_init(I2C_PMIC);
> if (!p)
> return -ENODEV;
>
> - ret = pfuze_mode_init(p, APS_PFM);
> - if (ret < 0)
> - return ret;
> + if (is_mx6dqp()) {
> + /* set SW2 staby volatage 0.975V*/
> + pmic_reg_read(p, PFUZE100_SW2STBY, &value);
> + value &= ~0x3f;
> + value |= 0x17;
> + pmic_reg_write(p, PFUZE100_SW2STBY, value);
> + }
>
> - return 0;
> + return pfuze_mode_init(p, APS_PFM);
> }
>
> #ifdef CONFIG_CMD_BMODE
> @@ -525,7 +542,9 @@ int board_late_init(void)
> #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> setenv("board_name", "SABREAUTO");
>
> - if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
> + if (is_mx6dqp())
> + setenv("board_rev", "MX6QP");
> + else if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
> setenv("board_rev", "MX6Q");
> else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO))
> setenv("board_rev", "MX6DL");
> diff --git a/configs/mx6qpsabreauto_defconfig b/configs/mx6qpsabreauto_defconfig
> new file mode 100644
> index 0000000..293e3f2
> --- /dev/null
> +++ b/configs/mx6qpsabreauto_defconfig
> @@ -0,0 +1,4 @@
> +CONFIG_ARM=y
> +CONFIG_TARGET_MX6QSABREAUTO=y
> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6qp.cfg,MX6Q"
> +CONFIG_SPI_FLASH=y
> diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
> index 903ab18..6722c9d 100644
> --- a/include/configs/mx6sabre_common.h
> +++ b/include/configs/mx6sabre_common.h
> @@ -148,6 +148,8 @@
> "fi;\0" \
> "findfdt="\
> "if test $fdt_file = undefined; then " \
> + "if test $board_name = SABREAUTO && test $board_rev = MX6QP; then " \
> + "setenv fdt_file imx6qp-sabreauto.dtb; fi; " \
> "if test $board_name = SABREAUTO && test $board_rev = MX6Q; then " \
> "setenv fdt_file imx6q-sabreauto.dtb; fi; " \
> "if test $board_name = SABREAUTO && test $board_rev = MX6DL; then " \
>
Applied to u-boot-imx, thanks !
Best regards,
Stefano Babic
--
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