[U-Boot] [PATCH 02/10] x86: minnowmax: Add access to GPIOs E0, E1, E2

[Simon Glass]

These GPIOs are accessible on the pin header. Add pinctrl settings for them
so that we they can be adjusted using the 'gpio' command.

Signed-off-by: Simon Glass <sjg at chromium.org>
---

 arch/x86/dts/minnowmax.dts | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index d0c0fe6..33fb009 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -29,6 +29,33 @@
 		compatible = "intel,x86-pinctrl";
 		io-base = <0x4c>;
 
+		/* GPIO E0 */
+		soc_gpio_s5_0 at 0 {
+			gpio-offset = <0x80 0>;
+			pad-offset = <0x1d0>;
+			mode-gpio;
+			output-value = <0>;
+			direction = <PIN_OUTPUT>;
+		};
+
+		/* GPIO E1 */
+		soc_gpio_s5_1 at 0 {
+			gpio-offset = <0x80 1>;
+			pad-offset = <0x210>;
+			mode-gpio;
+			output-value = <0>;
+			direction = <PIN_OUTPUT>;
+		};
+
+		/* GPIO E2 */
+		soc_gpio_s5_2 at 0 {
+			gpio-offset = <0x80 2>;
+			pad-offset = <0x1e0>;
+			mode-gpio;
+			output-value = <0>;
+			direction = <PIN_OUTPUT>;
+		};
+
 		pin_usb_host_en0 at 0 {
 			gpio-offset = <0x80 8>;
 			pad-offset = <0x260>;
-- 
2.5.0.276.gf5e568e