[U-Boot] [RFC PATCH 19/28] powerpc: remove MPC8540ADS support

Masahiro Yamada yamada.masahiro at socionext.com
Thu Aug 13 12:15:37 CEST 2015


This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)

Signed-off-by: Masahiro Yamada <yamada.masahiro at socionext.com>
---

 arch/powerpc/cpu/mpc85xx/Kconfig        |   4 -
 board/freescale/mpc8540ads/Kconfig      |  12 -
 board/freescale/mpc8540ads/MAINTAINERS  |   6 -
 board/freescale/mpc8540ads/Makefile     |  11 -
 board/freescale/mpc8540ads/ddr.c        |  46 ----
 board/freescale/mpc8540ads/law.c        |  42 ---
 board/freescale/mpc8540ads/mpc8540ads.c | 242 -----------------
 board/freescale/mpc8540ads/tlb.c        |  95 -------
 configs/MPC8540ADS_defconfig            |   3 -
 include/configs/MPC8540ADS.h            | 448 --------------------------------
 10 files changed, 909 deletions(-)
 delete mode 100644 board/freescale/mpc8540ads/Kconfig
 delete mode 100644 board/freescale/mpc8540ads/MAINTAINERS
 delete mode 100644 board/freescale/mpc8540ads/Makefile
 delete mode 100644 board/freescale/mpc8540ads/ddr.c
 delete mode 100644 board/freescale/mpc8540ads/law.c
 delete mode 100644 board/freescale/mpc8540ads/mpc8540ads.c
 delete mode 100644 board/freescale/mpc8540ads/tlb.c
 delete mode 100644 configs/MPC8540ADS_defconfig
 delete mode 100644 include/configs/MPC8540ADS.h

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 8907b03..33123db 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -43,9 +43,6 @@ config TARGET_P5040DS
 config TARGET_MPC8536DS
 	bool "Support MPC8536DS"
 
-config TARGET_MPC8540ADS
-	bool "Support MPC8540ADS"
-
 config TARGET_MPC8541CDS
 	bool "Support MPC8541CDS"
 
@@ -154,7 +151,6 @@ source "board/freescale/bsc9132qds/Kconfig"
 source "board/freescale/c29xpcie/Kconfig"
 source "board/freescale/corenet_ds/Kconfig"
 source "board/freescale/mpc8536ds/Kconfig"
-source "board/freescale/mpc8540ads/Kconfig"
 source "board/freescale/mpc8541cds/Kconfig"
 source "board/freescale/mpc8544ds/Kconfig"
 source "board/freescale/mpc8548cds/Kconfig"
diff --git a/board/freescale/mpc8540ads/Kconfig b/board/freescale/mpc8540ads/Kconfig
deleted file mode 100644
index 35a8545..0000000
--- a/board/freescale/mpc8540ads/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8540ADS
-
-config SYS_BOARD
-	default "mpc8540ads"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "MPC8540ADS"
-
-endif
diff --git a/board/freescale/mpc8540ads/MAINTAINERS b/board/freescale/mpc8540ads/MAINTAINERS
deleted file mode 100644
index acc4821..0000000
--- a/board/freescale/mpc8540ads/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MPC8540ADS BOARD
-#M:	Kumar Gala <kumar.gala at freescale.com>
-S:	Orphan (since 2014-06)
-F:	board/freescale/mpc8540ads/
-F:	include/configs/MPC8540ADS.h
-F:	configs/MPC8540ADS_defconfig
diff --git a/board/freescale/mpc8540ads/Makefile b/board/freescale/mpc8540ads/Makefile
deleted file mode 100644
index 6f82c7f..0000000
--- a/board/freescale/mpc8540ads/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	+= mpc8540ads.o
-obj-y	+= ddr.o
-obj-y	+= law.o
-obj-y	+= tlb.o
diff --git a/board/freescale/mpc8540ads/ddr.c b/board/freescale/mpc8540ads/ddr.c
deleted file mode 100644
index 41d4cfe..0000000
--- a/board/freescale/mpc8540ads/ddr.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	/*
-	 * Factors to consider for CPO:
-	 *	- frequency
-	 *	- ddr1 vs. ddr2
-	 */
-	popts->cpo_override = 0;
-
-	/*
-	 * Factors to consider for write data delay:
-	 *	- number of DIMMs
-	 *
-	 * 1 = 1/4 clock delay
-	 * 2 = 1/2 clock delay
-	 * 3 = 3/4 clock delay
-	 * 4 = 1   clock delay
-	 * 5 = 5/4 clock delay
-	 * 6 = 3/2 clock delay
-	 */
-	popts->write_data_delay = 3;
-
-	/* 2T timing enable */
-	popts->twot_en = 1;
-
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
-	 */
-	popts->half_strength_driver_enable = 0;
-}
diff --git a/board/freescale/mpc8540ads/law.c b/board/freescale/mpc8540ads/law.c
deleted file mode 100644
index 41f2e02..0000000
--- a/board/freescale/mpc8540ads/law.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * LAW(Local Access Window) configuration:
- *
- * 0x0000_0000     0x7fff_ffff     DDR                     2G
- * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
- * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
- * 0xe000_0000     0xe000_ffff     CCSR                    1M
- * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
- * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
- * 0xf800_0000     0xf80f_ffff     BCSR                    1M
- * 0xff00_0000     0xffff_ffff     FLASH (boot bank)       16M
- *
- * Notes:
- *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- *    If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-struct law_entry law_table[] = {
-#ifndef CONFIG_SPD_EEPROM
-	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
-#endif
-	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
-	/* This is not so much the SDRAM map as it is the whole localbus map. */
-	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
-	SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c
deleted file mode 100644
index 1069e2c..0000000
--- a/board/freescale/mpc8540ads/mpc8540ads.c
+++ /dev/null
@@ -1,242 +0,0 @@
-/*
- * Copyright 2004 Freescale Semiconductor.
- * (C) Copyright 2002,2003, Motorola Inc.
- * Xianghua Xiao, (X.Xiao at motorola.com)
- *
- * (C) Copyright 2002 Scott McNutt <smcnutt at artesyncp.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-
-#include <common.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <fsl_ddr_sdram.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
-void local_bus_init(void);
-
-int checkboard (void)
-{
-	puts("Board: ADS\n");
-
-#ifdef CONFIG_PCI
-	printf("PCI1: 32 bit, %d MHz (compiled)\n",
-	       CONFIG_SYS_CLK_FREQ / 1000000);
-#else
-	printf("PCI1: disabled\n");
-#endif
-
-	/*
-	 * Initialize local bus.
-	 */
-	local_bus_init();
-
-	return 0;
-}
-
-/*
- * Initialize Local Bus
- */
-
-void
-local_bus_init(void)
-{
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
-
-	uint clkdiv;
-	uint lbc_hz;
-	sys_info_t sysinfo;
-
-	/*
-	 * Errata LBC11.
-	 * Fix Local Bus clock glitch when DLL is enabled.
-	 *
-	 * If localbus freq is < 66MHz, DLL bypass mode must be used.
-	 * If localbus freq is > 133MHz, DLL can be safely enabled.
-	 * Between 66 and 133, the DLL is enabled with an override workaround.
-	 */
-
-	get_sys_info(&sysinfo);
-	clkdiv = lbc->lcrr & LCRR_CLKDIV;
-	lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv;
-
-	if (lbc_hz < 66) {
-		lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP;	/* DLL Bypass */
-
-	} else if (lbc_hz >= 133) {
-		lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
-
-	} else {
-		/*
-		 * On REV1 boards, need to change CLKDIV before enable DLL.
-		 * Default CLKDIV is 8, change it to 4 temporarily.
-		 */
-		uint pvr = get_pvr();
-		uint temp_lbcdll = 0;
-
-		if (pvr == PVR_85xx_REV1) {
-			/* FIXME: Justify the high bit here. */
-			lbc->lcrr = 0x10000004;
-		}
-
-		lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
-		udelay(200);
-
-		/*
-		 * Sample LBC DLL ctrl reg, upshift it to set the
-		 * override bits.
-		 */
-		temp_lbcdll = gur->lbcdllcr;
-		gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
-		asm("sync;isync;msync");
-	}
-}
-
-
-/*
- * Initialize SDRAM memory on the Local Bus.
- */
-void lbc_sdram_init(void)
-{
-	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
-	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
-
-	puts("LBC SDRAM: ");
-	print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
-		   "\n       ");
-
-	/*
-	 * Setup SDRAM Base and Option Registers
-	 */
-	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
-	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
-	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
-	asm("msync");
-
-	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
-	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
-	asm("sync");
-
-	/*
-	 * Configure the SDRAM controller.
-	 */
-	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
-	asm("sync");
-	*sdram_addr = 0xff;
-	ppcDcbf((unsigned long) sdram_addr);
-	udelay(100);
-
-	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
-	asm("sync");
-	*sdram_addr = 0xff;
-	ppcDcbf((unsigned long) sdram_addr);
-	udelay(100);
-
-	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;
-	asm("sync");
-	*sdram_addr = 0xff;
-	ppcDcbf((unsigned long) sdram_addr);
-	udelay(100);
-
-	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
-	asm("sync");
-	*sdram_addr = 0xff;
-	ppcDcbf((unsigned long) sdram_addr);
-	udelay(100);
-
-	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;
-	asm("sync");
-	*sdram_addr = 0xff;
-	ppcDcbf((unsigned long) sdram_addr);
-	udelay(100);
-}
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*************************************************************************
- *  fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-phys_size_t fixed_sdram(void)
-{
-  #ifndef CONFIG_SYS_RAMBOOT
-	struct ccsr_ddr __iomem *ddr =
-		(struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
-
-	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
-	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
-	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-	ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
-	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-    #if defined (CONFIG_DDR_ECC)
-	ddr->err_disable = 0x0000000D;
-	ddr->err_sbe = 0x00ff0000;
-    #endif
-	asm("sync;isync;msync");
-	udelay(500);
-    #if defined (CONFIG_DDR_ECC)
-	/* Enable ECC checking */
-	ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
-    #else
-	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
-    #endif
-	asm("sync; isync; msync");
-	udelay(500);
-  #endif
-	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-}
-#endif	/* !defined(CONFIG_SPD_EEPROM) */
-
-
-#if defined(CONFIG_PCI)
-/*
- * Initialize PCI Devices, report devices found.
- */
-
-
-static struct pci_controller hose;
-
-#endif	/* CONFIG_PCI */
-
-
-void
-pci_init_board(void)
-{
-#ifdef CONFIG_PCI
-	pci_mpc85xx_init(&hose);
-#endif /* CONFIG_PCI */
-}
-
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	int node, tmp[2];
-	const char *path;
-
-	ft_cpu_setup(blob, bd);
-
-	node = fdt_path_offset(blob, "/aliases");
-	tmp[0] = 0;
-	if (node >= 0) {
-#ifdef CONFIG_PCI
-		path = fdt_getprop(blob, node, "pci0", NULL);
-		if (path) {
-			tmp[1] = hose.last_busno - hose.first_busno;
-			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
-		}
-#endif
-	}
-
-	return 0;
-}
-#endif
diff --git a/board/freescale/mpc8540ads/tlb.c b/board/freescale/mpc8540ads/tlb.c
deleted file mode 100644
index d5ee791..0000000
--- a/board/freescale/mpc8540ads/tlb.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-
-	/*
-	 * TLB 0:	16M	Non-cacheable, guarded
-	 * 0xff000000	16M	FLASH
-	 * Out of reset this entry is only 4K.
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_16M, 1),
-
-	/*
-	 * TLB 1:	256M	Non-cacheable, guarded
-	 * 0x80000000	256M	PCI1 MEM First half
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 1, BOOKE_PAGESZ_256M, 1),
-
-	/*
-	 * TLB 2:	256M	Non-cacheable, guarded
-	 * 0x90000000	256M	PCI1 MEM Second half
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 2, BOOKE_PAGESZ_256M, 1),
-
-	/*
-	 * TLB 3:	256M	Non-cacheable, guarded
-	 * 0xc0000000	256M	Rapid IO MEM First half
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 3, BOOKE_PAGESZ_256M, 1),
-
-	/*
-	 * TLB 4:	256M	Non-cacheable, guarded
-	 * 0xd0000000	256M	Rapid IO MEM Second half
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 4, BOOKE_PAGESZ_256M, 1),
-
-	/*
-	 * TLB 5:	64M	Non-cacheable, guarded
-	 * 0xe000_0000	1M	CCSRBAR
-	 * 0xe200_0000	16M	PCI1 IO
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 5, BOOKE_PAGESZ_64M, 1),
-
-	/*
-	 * TLB 6:	64M	Cacheable, non-guarded
-	 * 0xf000_0000	64M	LBC SDRAM
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 6, BOOKE_PAGESZ_64M, 1),
-
-	/*
-	 * TLB 7:	16K	Non-cacheable, guarded
-	 * 0xf8000000	16K	BCSR registers
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 7, BOOKE_PAGESZ_16K, 1),
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/MPC8540ADS_defconfig b/configs/MPC8540ADS_defconfig
deleted file mode 100644
index 41af349..0000000
--- a/configs/MPC8540ADS_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_MPC8540ADS=y
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
deleted file mode 100644
index 931816b..0000000
--- a/include/configs/MPC8540ADS.h
+++ /dev/null
@@ -1,448 +0,0 @@
-/*
- * Copyright 2004, 2011 Freescale Semiconductor.
- * (C) Copyright 2002,2003 Motorola,Inc.
- * Xianghua Xiao <X.Xiao at motorola.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * mpc8540ads board configuration file
- *
- * Please refer to doc/README.mpc85xx for more info.
- *
- * Make sure you change the MAC address and other network params first,
- * search for CONFIG_SERVERIP, etc in this file.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* High Level Configuration Options */
-#define CONFIG_BOOKE		1	/* BOOKE */
-#define CONFIG_E500		1	/* BOOKE e500 family */
-#define CONFIG_MPC8540		1	/* MPC8540 specific */
-#define CONFIG_MPC8540ADS	1	/* MPC8540ADS board specific */
-
-/*
- * default CCARBAR is at 0xff700000
- * assume U-Boot is less than 0.5MB
- */
-#define	CONFIG_SYS_TEXT_BASE	0xfff80000
-
-#ifndef CONFIG_HAS_FEC
-#define CONFIG_HAS_FEC		1	/* 8540 has FEC */
-#endif
-
-#define CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
-#define CONFIG_TSEC_ENET		/* tsec ethernet support */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
-
-/*
- * sysclk for MPC85xx
- *
- * Two valid values are:
- *    33000000
- *    66000000
- *
- * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
- * is likely the desired value here, so that is now the default.
- * The board, however, can run at 66MHz.  In any event, this value
- * must match the settings of some switches.  Details can be found
- * in the README.mpc85xxads.
- *
- * XXX -- Can't we run at 66 MHz, anyway?  PCI should drop to
- * 33MHz to accommodate, based on a PCI pin.
- * Note that PCI-X won't work at 33MHz.
- */
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ	33000000
-#endif
-
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE			/* toggle L2 cache */
-#define CONFIG_BTB			/* toggle branch predition */
-
-#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
-#define CONFIG_SYS_MEMTEST_END		0x00400000
-
-#define CONFIG_SYS_CCSRBAR		0xe0000000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
-
-/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR1
-#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_SPD
-#undef CONFIG_FSL_DDR_INTERACTIVE
-
-#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
-
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_NUM_DDR_CONTROLLERS	1
-#define CONFIG_DIMM_SLOTS_PER_CTLR	1
-#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-
-/* I2C addresses of SPD EEPROMs */
-#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
-
-/* These are used when DDR doesn't use SPD. */
-#define CONFIG_SYS_SDRAM_SIZE	128		/* DDR is 128MB */
-#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007	/* 0-128MB */
-#define CONFIG_SYS_DDR_CS0_CONFIG	0x80000002
-#define CONFIG_SYS_DDR_TIMING_1	0x37344321
-#define CONFIG_SYS_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
-#define CONFIG_SYS_DDR_CONTROL		0xc2000000	/* unbuffered,no DYN_PWR */
-#define CONFIG_SYS_DDR_MODE		0x00000062	/* DLL,normal,seq,4/2.5 */
-#define CONFIG_SYS_DDR_INTERVAL	0x05200100	/* autocharge,no open page */
-
-/*
- * SDRAM on the Local Bus
- */
-#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
-#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
-
-#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of FLASH 16M */
-#define CONFIG_SYS_BR0_PRELIM		0xff001801	/* port size 32bit */
-
-#define CONFIG_SYS_OR0_PRELIM		0xff006ff7	/* 16MB Flash */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	64		/* sectors per device */
-#undef	CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef  CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#undef CONFIG_CLOCKS_IN_MHZ
-
-
-/*
- * Local Bus Definitions
- */
-
-/*
- * Base Register 2 and Option Register 2 configure SDRAM.
- * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
- *
- * For BR2, need:
- *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
- *    port-size = 32-bits = BR2[19:20] = 11
- *    no parity checking = BR2[21:22] = 00
- *    SDRAM for MSEL = BR2[24:26] = 011
- *    Valid = BR[31] = 1
- *
- * 0    4    8    12   16   20   24   28
- * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
- *
- * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
- * FIXME: the top 17 bits of BR2.
- */
-
-#define CONFIG_SYS_BR2_PRELIM		0xf0001861
-
-/*
- * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
- *
- * For OR2, need:
- *    64MB mask for AM, OR2[0:7] = 1111 1100
- *		   XAM, OR2[17:18] = 11
- *    9 columns OR2[19-21] = 010
- *    13 rows   OR2[23-25] = 100
- *    EAD set for extra time OR[31] = 1
- *
- * 0    4    8    12   16   20   24   28
- * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
- */
-
-#define CONFIG_SYS_OR2_PRELIM		0xfc006901
-
-#define CONFIG_SYS_LBC_LCRR		0x00030004    /* LB clock ratio reg */
-#define CONFIG_SYS_LBC_LBCR		0x00000000    /* LB config reg */
-#define CONFIG_SYS_LBC_LSRT		0x20000000    /* LB sdram refresh timer */
-#define CONFIG_SYS_LBC_MRTPR		0x20000000    /* LB refresh timer prescal*/
-
-#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_BSMA1516	\
-				| LSDMR_RFCR5		\
-				| LSDMR_PRETOACT3	\
-				| LSDMR_ACTTORW3	\
-				| LSDMR_BL8		\
-				| LSDMR_WRC2		\
-				| LSDMR_CL3		\
-				| LSDMR_RFEN		\
-				)
-
-/*
- * SDRAM Controller configuration sequence.
- */
-#define CONFIG_SYS_LBC_LSDMR_1	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
-#define CONFIG_SYS_LBC_LSDMR_2	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_3	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_4	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
-#define CONFIG_SYS_LBC_LSDMR_5	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
-
-
-/*
- * 32KB, 8-bit wide for ADS config reg
- */
-#define CONFIG_SYS_BR4_PRELIM          0xf8000801
-#define CONFIG_SYS_OR4_PRELIM		0xffffe1f1
-#define CONFIG_SYS_BCSR		(CONFIG_SYS_BR4_PRELIM & 0xffff8000)
-
-#define CONFIG_SYS_INIT_RAM_LOCK	1
-#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)    /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)    /* Reserved for malloc */
-
-/* Serial Port */
-#define CONFIG_CONS_INDEX     1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE    1
-#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE  \
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
-
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-#ifdef  CONFIG_SYS_HUSH_PARSER
-#endif
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT		1
-#define CONFIG_OF_BOARD_SETUP		1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED	400000
-#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
-#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
-
-/* RapidIO MMU */
-#define CONFIG_SYS_RIO_MEM_VIRT	0xc0000000	/* base address */
-#define CONFIG_SYS_RIO_MEM_BUS	0xc0000000	/* base address */
-#define CONFIG_SYS_RIO_MEM_PHYS	0xc0000000
-#define CONFIG_SYS_RIO_MEM_SIZE	0x20000000	/* 128M */
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
-#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
-#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCI1_IO_VIRT	0xe2000000
-#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
-#define CONFIG_SYS_PCI1_IO_SIZE	0x100000	/* 1M */
-
-#if defined(CONFIG_PCI)
-
-#define CONFIG_PCI_PNP			/* do pci plug-and-play */
-
-#undef CONFIG_EEPRO100
-#undef CONFIG_TULIP
-
-#if !defined(CONFIG_PCI_PNP)
-    #define PCI_ENET0_IOADDR	0xe0000000
-    #define PCI_ENET0_MEMADDR	0xe0000000
-    #define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
-#endif
-
-#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
-
-#endif	/* CONFIG_PCI */
-
-
-#if defined(CONFIG_TSEC_ENET)
-
-#define CONFIG_MII		1	/* MII PHY management */
-#define CONFIG_TSEC1	1
-#define CONFIG_TSEC1_NAME	"TSEC0"
-#define CONFIG_TSEC2	1
-#define CONFIG_TSEC2_NAME	"TSEC1"
-#define TSEC1_PHY_ADDR		0
-#define TSEC2_PHY_ADDR		1
-#define TSEC1_PHYIDX		0
-#define TSEC2_PHYIDX		0
-#define TSEC1_FLAGS		TSEC_GIGABIT
-#define TSEC2_FLAGS		TSEC_GIGABIT
-
-
-#if CONFIG_HAS_FEC
-#define CONFIG_MPC85XX_FEC	1
-#define CONFIG_MPC85XX_FEC_NAME		"FEC"
-#define FEC_PHY_ADDR		3
-#define FEC_PHYIDX		0
-#define FEC_FLAGS		0
-#endif
-
-/* Options are: TSEC[0-1], FEC */
-#define CONFIG_ETHPRIME		"TSEC0"
-
-#endif	/* CONFIG_TSEC_ENET */
-
-
-/*
- * Environment
- */
-#ifndef CONFIG_SYS_RAMBOOT
-  #define CONFIG_ENV_IS_IN_FLASH	1
-  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
-  #define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
-  #define CONFIG_ENV_SIZE		0x2000
-#else
-  #define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now */
-  #define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
-  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
-  #define CONFIG_ENV_SIZE		0x2000
-#endif
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_IRQ
-
-#if defined(CONFIG_PCI)
-    #define CONFIG_CMD_PCI
-#endif
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
-#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
-#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
-#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-
-#if defined(CONFIG_CMD_KGDB)
-    #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
-#else
-    #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
-#endif
-
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#endif
-
-
-/*
- * Environment Configuration
- */
-
-/* The mac addresses for all ethernet interface */
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
-#endif
-
-#define CONFIG_IPADDR    192.168.1.253
-
-#define CONFIG_HOSTNAME		unknown
-#define CONFIG_ROOTPATH		"/nfsroot"
-#define CONFIG_BOOTFILE		"your.uImage"
-
-#define CONFIG_SERVERIP  192.168.1.1
-#define CONFIG_GATEWAYIP 192.168.1.1
-#define CONFIG_NETMASK   255.255.255.0
-
-#define CONFIG_LOADADDR  200000	/* default location for tftp and bootm */
-
-#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
-#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
-
-#define CONFIG_BAUDRATE	115200
-
-#define	CONFIG_EXTRA_ENV_SETTINGS				        \
-   "netdev=eth0\0"                                                      \
-   "consoledev=ttyS0\0"                                                 \
-   "ramdiskaddr=1000000\0"						\
-   "ramdiskfile=your.ramdisk.u-boot\0"					\
-   "fdtaddr=400000\0"							\
-   "fdtfile=your.fdt.dtb\0"
-
-#define CONFIG_NFSBOOTCOMMAND	                                        \
-   "setenv bootargs root=/dev/nfs rw "                                  \
-      "nfsroot=$serverip:$rootpath "                                    \
-      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
-      "console=$consoledev,$baudrate $othbootargs;"                     \
-   "tftp $loadaddr $bootfile;"                                          \
-   "tftp $fdtaddr $fdtfile;"						\
-   "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
-   "setenv bootargs root=/dev/ram rw "                                  \
-      "console=$consoledev,$baudrate $othbootargs;"                     \
-   "tftp $ramdiskaddr $ramdiskfile;"                                    \
-   "tftp $loadaddr $bootfile;"                                          \
-   "tftp $fdtaddr $fdtfile;"						\
-   "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
-
-#endif	/* __CONFIG_H */
-- 
1.9.1



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