[U-Boot] [RFC PATCH 16/28] powerpc: remove v38b support

Masahiro Yamada yamada.masahiro at socionext.com
Thu Aug 13 12:15:34 CEST 2015


This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)

Signed-off-by: Masahiro Yamada <yamada.masahiro at socionext.com>
---

 arch/powerpc/cpu/mpc5xxx/Kconfig |   4 -
 board/v38b/Kconfig               |   9 --
 board/v38b/MAINTAINERS           |   6 -
 board/v38b/Makefile              |   8 -
 board/v38b/ethaddr.c             | 197 -----------------------
 board/v38b/v38b.c                | 260 ------------------------------
 configs/v38b_defconfig           |   4 -
 include/configs/v38b.h           | 333 ---------------------------------------
 8 files changed, 821 deletions(-)
 delete mode 100644 board/v38b/Kconfig
 delete mode 100644 board/v38b/MAINTAINERS
 delete mode 100644 board/v38b/Makefile
 delete mode 100644 board/v38b/ethaddr.c
 delete mode 100644 board/v38b/v38b.c
 delete mode 100644 configs/v38b_defconfig
 delete mode 100644 include/configs/v38b.h

diff --git a/arch/powerpc/cpu/mpc5xxx/Kconfig b/arch/powerpc/cpu/mpc5xxx/Kconfig
index dc86ac3..7fa948f 100644
--- a/arch/powerpc/cpu/mpc5xxx/Kconfig
+++ b/arch/powerpc/cpu/mpc5xxx/Kconfig
@@ -18,9 +18,6 @@ config TARGET_A4M072
 config TARGET_CM5200
 	bool "Support cm5200"
 
-config TARGET_V38B
-	bool "Support v38b"
-
 config TARGET_O2D
 	bool "Support O2D"
 
@@ -56,6 +53,5 @@ source "board/cm5200/Kconfig"
 source "board/ifm/o2dnt2/Kconfig"
 source "board/intercontrol/digsy_mtc/Kconfig"
 source "board/tqc/tqm5200/Kconfig"
-source "board/v38b/Kconfig"
 
 endmenu
diff --git a/board/v38b/Kconfig b/board/v38b/Kconfig
deleted file mode 100644
index 653bfc1..0000000
--- a/board/v38b/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_V38B
-
-config SYS_BOARD
-	default "v38b"
-
-config SYS_CONFIG_NAME
-	default "v38b"
-
-endif
diff --git a/board/v38b/MAINTAINERS b/board/v38b/MAINTAINERS
deleted file mode 100644
index d1a6ae6..0000000
--- a/board/v38b/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-V38B BOARD
-#M:	-
-S:	Maintained
-F:	board/v38b/
-F:	include/configs/v38b.h
-F:	configs/v38b_defconfig
diff --git a/board/v38b/Makefile b/board/v38b/Makefile
deleted file mode 100644
index a20a5ef..0000000
--- a/board/v38b/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= v38b.o ethaddr.o
diff --git a/board/v38b/ethaddr.c b/board/v38b/ethaddr.c
deleted file mode 100644
index 982998f..0000000
--- a/board/v38b/ethaddr.c
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * (C) Copyright 2006
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-
-/* For the V38B board the pin is GPIO_PSC_6 */
-#define GPIO_PIN	GPIO_PSC6_0
-
-#define NO_ERROR	0
-#define ERR_NO_NUMBER	1
-#define ERR_BAD_NUMBER	2
-
-static int is_high(void);
-static int check_device(void);
-static void io_out(int value);
-static void io_input(void);
-static void io_output(void);
-static void init_gpio(void);
-static void read_byte(unsigned char *data);
-static void write_byte(unsigned char command);
-
-void read_2501_memory(unsigned char *psernum, unsigned char *perr);
-void board_get_enetaddr(uchar *enetaddr);
-
-
-static int is_high()
-{
-	return (*((vu_long *) MPC5XXX_WU_GPIO_DATA_I) & GPIO_PIN);
-}
-
-static void io_out(int value)
-{
-	if (value)
-		*((vu_long *) MPC5XXX_WU_GPIO_DATA_O) |= GPIO_PIN;
-	else
-		*((vu_long *) MPC5XXX_WU_GPIO_DATA_O) &= ~GPIO_PIN;
-}
-
-static void io_input()
-{
-	*((vu_long *) MPC5XXX_WU_GPIO_DIR) &= ~GPIO_PIN;
-	udelay(3);	/* allow input to settle */
-}
-
-static void io_output()
-{
-	*((vu_long *) MPC5XXX_WU_GPIO_DIR) |= GPIO_PIN;
-}
-
-static void init_gpio()
-{
-	*((vu_long *) MPC5XXX_WU_GPIO_ENABLE) |= GPIO_PIN;	/* Enable appropriate pin */
-}
-
-void read_2501_memory(unsigned char *psernum, unsigned char *perr)
-{
-#define NBYTES 28
-	unsigned char crcval, i;
-	unsigned char buf[NBYTES];
-
-	*perr = 0;
-	crcval = 0;
-
-	for (i = 0; i < NBYTES; i++)
-		buf[i] = 0;
-
-	if (!check_device())
-		*perr = ERR_NO_NUMBER;
-	else {
-		*perr = NO_ERROR;
-		write_byte(0xCC);		/* skip ROM (0xCC) */
-		write_byte(0xF0);		/* Read memory command 0xF0 */
-		write_byte(0x00);		/* Address TA1=0, TA2=0 */
-		write_byte(0x00);
-		read_byte(&crcval);		/* Read CRC of address and command */
-
-		for (i = 0; i < NBYTES; i++)
-			read_byte(&buf[i]);
-	}
-	if (strncmp((const char *) &buf[11], "MAREL IEEE 802.3", 16)) {
-		*perr = ERR_BAD_NUMBER;
-		psernum[0] = 0x00;
-		psernum[1] = 0xE0;
-		psernum[2] = 0xEE;
-		psernum[3] = 0xFF;
-		psernum[4] = 0xFF;
-		psernum[5] = 0xFF;
-	} else {
-		psernum[0] = 0x00;
-		psernum[1] = 0xE0;
-		psernum[2] = 0xEE;
-		psernum[3] = buf[7];
-		psernum[4] = buf[6];
-		psernum[5] = buf[5];
-	}
-}
-
-static int check_device()
-{
-	int found;
-
-	io_output();
-	io_out(0);
-	udelay(500);  /* must be at least 480 us low pulse */
-
-	io_input();
-	udelay(60);
-
-	found = (is_high() == 0) ? 1 : 0;
-	udelay(500);  /* must be at least 480 us low pulse */
-
-	return found;
-}
-
-static void write_byte(unsigned char command)
-{
-	char i;
-
-	for (i = 0; i < 8; i++) {
-		/* 1 us to 15 us low pulse starts bit slot */
-		/* Start with high pulse for 3 us */
-		io_input();
-		udelay(3);
-
-		io_out(0);
-		io_output();
-		udelay(3);
-
-		if (command & 0x01) {
-			/* 60 us high for 1-bit */
-			io_input();
-			udelay(60);
-		} else
-			/* 60 us low for 0-bit */
-			udelay(60);
-		/*  Leave pin as input */
-		io_input();
-
-		command = command >> 1;
-	}
-}
-
-static void read_byte(unsigned char *data)
-{
-	unsigned char i, rdat = 0;
-
-	for (i = 0; i < 8; i++) {
-		/* read one bit from one-wire device */
-
-		/* 1 - 15 us low starts bit slot */
-		io_out(0);
-		io_output();
-		udelay(0);
-
-		/* allow line to be pulled high */
-		io_input();
-
-		/* delay 10 us */
-		udelay(10);
-
-		/* now sample input status */
-		if (is_high())
-			rdat = (rdat >> 1) | 0x80;
-		else
-			rdat = rdat >> 1;
-
-		udelay(60);	/* at least 60 us */
-	}
-	/* copy the return value */
-	*data = rdat;
-}
-
-void board_get_enetaddr(uchar *enetaddr)
-{
-	unsigned char sn[6], err = NO_ERROR;
-
-	init_gpio();
-
-	read_2501_memory(sn, &err);
-
-	if (err == NO_ERROR) {
-		sprintf((char *)enetaddr, "%02x:%02x:%02x:%02x:%02x:%02x",
-				sn[0], sn[1], sn[2], sn[3], sn[4], sn[5]);
-		printf("MAC address: %s\n", enetaddr);
-		setenv("ethaddr", (char *)enetaddr);
-	} else {
-		sprintf((char *)enetaddr, "00:01:02:03:04:05");
-		printf("Error reading MAC address.\n");
-		printf("Setting default to %s\n", enetaddr);
-		setenv("ethaddr", (char *)enetaddr);
-	}
-}
diff --git a/board/v38b/v38b.c b/board/v38b/v38b.c
deleted file mode 100644
index a337729..0000000
--- a/board/v38b/v38b.c
+++ /dev/null
@@ -1,260 +0,0 @@
-/*
- * (C) Copyright 2003-2006
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas at motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <net.h>
-#include <asm/processor.h>
-
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start(int hi_addr)
-{
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
-	/* unlock mode register */
-	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* precharge all banks */
-	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-#if SDRAM_DDR
-	/* set mode register: extended mode */
-	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
-	__asm__ volatile ("sync");
-
-	/* set mode register: reset DLL */
-	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
-	__asm__ volatile ("sync");
-#endif /* SDRAM_DDR */
-
-	/* precharge all banks */
-	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* auto refresh */
-	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* set mode register */
-	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
-	__asm__ volatile ("sync");
-
-	/* normal operation */
-	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
-	__asm__ volatile ("sync");
-}
-#endif /* !CONFIG_SYS_RAMBOOT */
-
-
-phys_size_t initdram(int board_type)
-{
-	ulong dramsize = 0;
-	ulong dramsize2 = 0;
-	uint svr, pvr;
-
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* setup SDRAM chip selects */
-	*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e;	/* 2G at 0x0 */
-	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000;	/* disabled */
-	__asm__ volatile ("sync");
-
-	/* setup config registers */
-	*(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
-	*(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
-	__asm__ volatile ("sync");
-
-#if SDRAM_DDR
-	/* set tap delay */
-	*(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
-	__asm__ volatile ("sync");
-#endif /* SDRAM_DDR */
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else
-		dramsize = test2;
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20))
-		dramsize = 0;
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0)
-		*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
-	else
-		*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
-
-	/* let SDRAM CS1 start right after CS0 */
-	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
-
-	/* find RAM size using SDRAM CS1 only */
-	if (!dramsize)
-		sdram_start(0);
-	test2 = test1 = get_ram_size((long *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
-	if (!dramsize) {
-		sdram_start(1);
-		test2 = get_ram_size((long *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
-	}
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize2 = test1;
-	} else
-		dramsize2 = test2;
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize2 < (1 << 20))
-		dramsize2 = 0;
-
-	/* set SDRAM CS1 size according to the amount of RAM found */
-	if (dramsize2 > 0)
-		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize
-			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
-	else
-		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
-
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* retrieve size of memory connected to SDRAM CS0 */
-	dramsize = *(vu_long *) MPC5XXX_SDRAM_CS0CFG & 0xFF;
-	if (dramsize >= 0x13)
-		dramsize = (1 << (dramsize - 0x13)) << 20;
-	else
-		dramsize = 0;
-
-	/* retrieve size of memory connected to SDRAM CS1 */
-	dramsize2 = *(vu_long *) MPC5XXX_SDRAM_CS1CFG & 0xFF;
-	if (dramsize2 >= 0x13)
-		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
-	else
-		dramsize2 = 0;
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	/*
-	 * On MPC5200B we need to set the special configuration delay in the
-	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
-	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
-	 *
-	 * "The SDelay should be written to a value of 0x00000004. It is
-	 * required to account for changes caused by normal wafer processing
-	 * parameters."
-	 */
-	svr = get_svr();
-	pvr = get_pvr();
-	if ((SVR_MJREV(svr) >= 2) &&
-		(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
-
-		*(vu_long *) MPC5XXX_SDRAM_SDELAY = 0x04;
-		__asm__ volatile ("sync");
-	}
-
-	return dramsize + dramsize2;
-}
-
-
-int checkboard (void)
-{
-	puts("Board: MarelV38B\n");
-	return 0;
-}
-
-int board_early_init_f(void)
-{
-#ifdef CONFIG_HW_WATCHDOG
-	/*
-	 * Enable and configure the direction (output) of PSC3_9 - watchdog
-	 * reset input. Refer to 7.3.2.2.[1,3,4] of the MPC5200B User's
-	 * Manual.
-	 */
-	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9;
-	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC3_9;
-#endif /* CONFIG_HW_WATCHDOG */
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-	/*
-	 * Now, when we are in RAM, enable flash write access for the
-	 * detection process.  Note that CS_BOOT cannot be cleared when
-	 * executing in flash.
-	 */
-	*(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
-
-	/*
-	 * Enable GPIO_WKUP_7 to "read the status of the actual power
-	 * situation". Default direction is input, so no need to set it
-	 * explicitly.
-	 */
-	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WKUP_7;
-	return 0;
-}
-
-extern void board_get_enetaddr(uchar *enetaddr);
-int misc_init_r(void)
-{
-	uchar enetaddr[6];
-
-	if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
-		board_get_enetaddr(enetaddr);
-		eth_setenv_enetaddr("ethaddr", enetaddr);
-	}
-
-	return 0;
-}
-
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
-void init_ide_reset(void)
-{
-	debug("init_ide_reset\n");
-
-	/* Configure PSC1_4 as GPIO output for ATA reset */
-	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
-	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
-	/* Deassert reset */
-	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
-}
-
-
-void ide_set_reset(int idereset)
-{
-	debug("ide_reset(%d)\n", idereset);
-
-	if (idereset) {
-		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
-		/* Make a delay. MPC5200 spec says 25 usec min */
-		udelay(500000);
-	} else
-		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC1_4;
-}
-#endif
-
-
-#ifdef CONFIG_HW_WATCHDOG
-void hw_watchdog_reset(void)
-{
-	/*
-	 * MarelV38B has a TPS3705 watchdog. Spec says that to kick the dog
-	 * we need a positive or negative transition on WDI i.e., our PSC3_9.
-	 */
-	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O ^= GPIO_PSC3_9;
-}
-#endif /* CONFIG_HW_WATCHDOG */
diff --git a/configs/v38b_defconfig b/configs/v38b_defconfig
deleted file mode 100644
index cc3d802..0000000
--- a/configs/v38b_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_V38B=y
-# CONFIG_CMD_SETEXPR is not set
diff --git a/include/configs/v38b.h b/include/configs/v38b.h
deleted file mode 100644
index 63049ab..0000000
--- a/include/configs/v38b.h
+++ /dev/null
@@ -1,333 +0,0 @@
-/*
- * (C) Copyright 2003-2006 Wolfgang Denk, DENX Software Engineering,
- * wd at denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MPC5200			1	/* This is an MPC5200 CPU */
-#define CONFIG_V38B			1	/* ...on V38B board */
-
-#define	CONFIG_SYS_TEXT_BASE		0xFF000000
-
-#define CONFIG_SYS_MPC5XXX_CLKIN	33000000	/* ...running at 33.000000MHz */
-
-#define CONFIG_RTC_PCF8563		1	/* has PCF8563 RTC */
-#define CONFIG_MPC5200_DDR		1	/* has DDR SDRAM */
-
-#undef CONFIG_HW_WATCHDOG			/* don't use watchdog */
-
-#define CONFIG_NETCONSOLE		1
-
-#define CONFIG_BOARD_EARLY_INIT_R	1	/* do board-specific init */
-#define CONFIG_BOARD_EARLY_INIT_F	1	/* do board-specific init */
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_SYS_XLB_PIPELINING		1	/* gives better performance */
-
-#define CONFIG_HIGH_BATS	1	/* High BATs supported */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
-#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * DDR
- */
-#define SDRAM_DDR		1	/* is DDR */
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE		0x018D0000
-#define SDRAM_EMODE		0x40090000
-#define SDRAM_CONTROL		0x704f0f00
-#define SDRAM_CONFIG1		0x73722930
-#define SDRAM_CONFIG2		0x47770000
-#define SDRAM_TAPDELAY		0x10000000
-
-/*
- * PCI - no suport
- */
-#undef CONFIG_PCI
-
-/*
- * Partitions
- */
-#define CONFIG_MAC_PARTITION	1
-#define CONFIG_DOS_PARTITION	1
-
-/*
- * USB
- */
-#define CONFIG_USB_OHCI
-#define CONFIG_USB_STORAGE
-#define CONFIG_USB_CLOCK	0x0001BBBB
-#define CONFIG_USB_CONFIG	0x00001000
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_USB
-#define CONFIG_CMD_FAT
-
-
-#define CONFIG_TIMESTAMP		/* Print image info with timestamp */
-
-/*
- * Boot low with 16 MB Flash
- */
-#define CONFIG_SYS_LOWBOOT		1
-#define CONFIG_SYS_LOWBOOT16		1
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds */
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	"bootcmd=run net_nfs\0"						\
-	"bootdelay=3\0"							\
-	"baudrate=115200\0"						\
-	"preboot=echo;echo Type \"run flash_nfs\" to mount root "	\
-		"filesystem over NFS; echo\0"				\
-	"netdev=eth0\0"							\
-	"ramargs=setenv bootargs root=/dev/ram rw wdt=off \0"		\
-	"addip=setenv bootargs $(bootargs) "				\
-		"ip=$(ipaddr):$(serverip):$(gatewayip):"		\
-		"$(netmask):$(hostname):$(netdev):off panic=1\0"	\
-	"flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0"		\
-	"flash_self=run ramargs addip;bootm $(kernel_addr) "		\
-		"$(ramdisk_addr)\0"					\
-	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=$(serverip):$(rootpath) wdt=off\0"		\
-	"hostname=v38b\0"						\
-	"ethact=FEC\0"							\
-	"rootpath=/opt/eldk-3.1.1/ppc_6xx\0"				\
-	"update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; "	\
-		"cp.b 200000 ff000000 $(filesize);"			\
-		"prot on ff000000 ff03ffff\0"				\
-	"load=tftp 200000 $(u-boot)\0"					\
-	"netmask=255.255.0.0\0"						\
-	"ipaddr=192.168.160.18\0"					\
-	"serverip=192.168.1.1\0"					\
-	"bootfile=/tftpboot/v38b/uImage\0"				\
-	"u-boot=/tftpboot/v38b/u-boot.bin\0"				\
-	""
-
-#define CONFIG_BOOTCOMMAND	"run net_nfs"
-
-/*
- * IPB Bus clocking configuration.
- */
-#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK			/* define for 133MHz speed */
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
-#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #1 or #2 */
-#define CONFIG_SYS_I2C_SPEED		100000	/* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE		0x7F
-
-/*
- * EEPROM configuration
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70
-
-/*
- * RTC configuration
- */
-#define CONFIG_SYS_I2C_RTC_ADDR		0x51
-
-/*
- * Flash configuration - use CFI driver
- */
-#define CONFIG_SYS_FLASH_CFI		1		/* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER	1		/* Use the common driver */
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET	1
-#define CONFIG_SYS_FLASH_BASE		0xFF000000
-#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* max num of flash banks */
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
-#define CONFIG_SYS_FLASH_SIZE		0x01000000	/* 16 MiB */
-#define CONFIG_SYS_MAX_FLASH_SECT	256		/* max num of sects on one chip */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1	/* flash write speed-up */
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00040000)
-#define CONFIG_ENV_SIZE		0x10000
-#define CONFIG_ENV_SECT_SIZE	0x10000
-#define CONFIG_ENV_OVERWRITE	1
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR		0xF0000000
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#   define CONFIG_SYS_RAMBOOT		1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Linux initial memory map */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC	1
-#define CONFIG_MPC5xxx_FEC_MII100
-#define CONFIG_PHY_ADDR		0x00
-#define CONFIG_MII		1
-
-/*
- * GPIO configuration
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x90001404
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
-
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG		0x00047801
-#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
-
-#define CONFIG_SYS_CS_BURST		0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
-
-#define CONFIG_SYS_RESET_ADDRESS	0xff000000
-
-/*
- * IDE/ATA (supports IDE harddisk)
- */
-#undef CONFIG_IDE_8xx_PCCARD		/* Don't use IDE with PC Card Adapter */
-#undef CONFIG_IDE_8xx_DIRECT		/* Direct IDE not supported */
-#undef CONFIG_IDE_LED			/* LED for ide not supported */
-
-#define CONFIG_IDE_RESET		/* reset for ide supported */
-#define CONFIG_IDE_PREINIT
-
-#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
-
-#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)	/* data I/O offset */
-
-#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)	/* normal register accesses offset */
-
-#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)	/* alternate registers offset */
-
-#define CONFIG_SYS_ATA_STRIDE		4		/* Interval between registers */
-
-/*
- * Status LED
- */
-#define  CONFIG_STATUS_LED		/* Status LED enabled */
-#define  CONFIG_BOARD_SPECIFIC_LED	/* version has board specific leds */
-
-#define CONFIG_SYS_LED_BASE	MPC5XXX_GPT7_ENABLE	/* Timer 7 GPIO */
-#ifndef __ASSEMBLY__
-typedef unsigned int led_id_t;
-
-#define __led_toggle(_msk) \
-	do { \
-		*((volatile long *) (CONFIG_SYS_LED_BASE)) ^= (_msk); \
-	} while(0)
-
-#define __led_set(_msk, _st) \
-	do { \
-		if ((_st)) \
-			*((volatile long *) (CONFIG_SYS_LED_BASE)) &= ~(_msk); \
-		else \
-			*((volatile long *) (CONFIG_SYS_LED_BASE)) |= (_msk); \
-	} while(0)
-
-#define __led_init(_msk, st) \
-	do { \
-		*((volatile long *) (CONFIG_SYS_LED_BASE)) |= 0x34; \
-	} while(0)
-#endif /* __ASSEMBLY__ */
-
-#endif /* __CONFIG_H */
-- 
1.9.1



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