[U-Boot] [U-Boot, V2, 1/3] ARM: Introduce erratum workaround for 801819

[Tom Rini]

On Mon, Jul 27, 2015 at 04:26:05PM -0500, Nishanth Menon wrote:

> Add workaround for Cortex-A15 ARM erratum 801819 which says in summary
> that "A livelock can occur in the L2 cache arbitration that might
> prevent a snoop from completing. Under certain conditions this can
> cause the system to deadlock. "
> 
> Recommended workaround is as follows:
> Do both of the following:
> 
> 1) Do not use the write-back no-allocate memory type.
> 2) Do not issue write-back cacheable stores at any time when the cache
> is disabled (SCTLR.C=0) and the MMU is enabled (SCTLR.M=1). Because it
> is implementation defined whether cacheable stores update the cache when
> the cache is disabled it is not expected that any portable code will
> execute cacheable stores when the cache is disabled.
> 
> For implementations of Cortex-A15 configured without the “L2 arbitration
> register slice” option (typically one or two core systems), you must
> also do the following:
> 
> 3) Disable write-streaming in each CPU by setting ACTLR[28:25] = 0b1111
> 
> So, we provide an option to disable write streaming on OMAP5 and DRA7.
> It is a rare condition to occur and may be enabled selectively based
> on platform acceptance of risk.
> 
> Applies to: A15 revisions r2p0, r2p1, r2p2, r2p3 or r2p4 and REVIDR[3]
> is set to 0.
> 
> Note: certain unicore SoCs *might* not have REVIDR[3] not set, but
> might not meet the condition for the erratum to occur when they donot
> have ACP (Accelerator Coherency Port) hooked to ACE (AXI Coherency
> Extensions). Such SoCs will need the work around handled in the SoC
> specific manner, since there is no ARM generic manner to detect such
> configurations.
> 
> Based on ARM errata Document revision 18.0 (22 Nov 2013)
> 
> Suggested-by: Richard Woodruff <r-woodruff2 at ti.com>
> Suggested-by: Brad Griffis <bgriffis at ti.com>
> Reviewed-by: Brad Griffis <bgriffis at ti.com>
> Signed-off-by: Nishanth Menon <nm at ti.com>

Applied to u-boot/master, thanks!

-- 
Tom
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