[U-Boot] [PATCH v4 1/2] x86: minnowmax: Define and enable interrupt setup

Bin Meng bmeng.cn at gmail.com
Fri Aug 14 08:26:09 CEST 2015


On Fri, Aug 14, 2015 at 12:36 AM, Simon Glass <sjg at chromium.org> wrote:
> Set up interrupts correctly so that Linux can use all devices. Use
> savedefconfig to regenerate the defconfig file.
>
> Signed-off-by: Simon Glass <sjg at chromium.org>
> ---
>
> Changes in v4:
> - Use the same interrupt routing as bayleybay
>
> Changes in v3:
> - Drop unnecessary blank lines
> - Add PCIe root ports from bayleybay
>
> Changes in v2:
> - Use pirq_init() instead of custom code
>
>  arch/x86/dts/minnowmax.dts  | 69 +++++++++++++++++++++++++++++++++++++++++++--
>  configs/minnowmax_defconfig |  3 +-
>  include/configs/minnowmax.h |  1 +
>  3 files changed, 69 insertions(+), 4 deletions(-)
>
> diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
> index d0c0fe6..daac24e 100644
> --- a/arch/x86/dts/minnowmax.dts
> +++ b/arch/x86/dts/minnowmax.dts
> @@ -7,6 +7,7 @@
>  /dts-v1/;
>
>  #include <dt-bindings/gpio/x86-gpio.h>
> +#include <dt-bindings/interrupt-router/intel-irq.h>
>
>  /include/ "skeleton.dtsi"
>  /include/ "serial.dtsi"
> @@ -117,9 +118,71 @@
>                 #address-cells = <3>;
>                 #size-cells = <2>;
>                 u-boot,dm-pre-reloc;
> -               ranges = <0x02000000 0x0 0xd0000000 0xd0000000 0 0x10000000
> -                       0x42000000 0x0 0xc0000000 0xc0000000 0 0x10000000
> -                       0x01000000 0x0 0x2000 0x2000 0 0xe000>;
> +               ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
> +                         0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
> +                         0x01000000 0x0 0x2000 0x2000 0 0xe000>;
> +
> +               irq-router at 1f,0 {
> +                       reg = <0x0000f800 0 0 0 0>;
> +                       compatible = "intel,irq-router";
> +                       intel,pirq-config = "ibase";
> +                       intel,ibase-offset = <0x50>;
> +                       intel,pirq-link = <8 8>;
> +                       intel,pirq-mask = <0xdee0>;
> +                       intel,pirq-routing = <
> +                               /* BayTrail PCI devices */
> +                               PCI_BDF(0, 2, 0) INTA PIRQA
> +                               PCI_BDF(0, 3, 0) INTA PIRQA
> +                               PCI_BDF(0, 16, 0) INTA PIRQA
> +                               PCI_BDF(0, 17, 0) INTA PIRQA
> +                               PCI_BDF(0, 18, 0) INTA PIRQA
> +                               PCI_BDF(0, 19, 0) INTA PIRQA
> +                               PCI_BDF(0, 20, 0) INTA PIRQA
> +                               PCI_BDF(0, 21, 0) INTA PIRQA
> +                               PCI_BDF(0, 22, 0) INTA PIRQA
> +                               PCI_BDF(0, 23, 0) INTA PIRQA
> +                               PCI_BDF(0, 24, 0) INTA PIRQA
> +                               PCI_BDF(0, 24, 1) INTC PIRQC
> +                               PCI_BDF(0, 24, 2) INTD PIRQD
> +                               PCI_BDF(0, 24, 3) INTB PIRQB
> +                               PCI_BDF(0, 24, 4) INTA PIRQA
> +                               PCI_BDF(0, 24, 5) INTC PIRQC
> +                               PCI_BDF(0, 24, 6) INTD PIRQD
> +                               PCI_BDF(0, 24, 7) INTB PIRQB
> +                               PCI_BDF(0, 26, 0) INTA PIRQA
> +                               PCI_BDF(0, 27, 0) INTA PIRQA
> +                               PCI_BDF(0, 28, 0) INTA PIRQA
> +                               PCI_BDF(0, 28, 1) INTB PIRQB
> +                               PCI_BDF(0, 28, 2) INTC PIRQC
> +                               PCI_BDF(0, 28, 3) INTD PIRQD
> +                               PCI_BDF(0, 29, 0) INTA PIRQA
> +                               PCI_BDF(0, 30, 0) INTA PIRQA
> +                               PCI_BDF(0, 30, 1) INTD PIRQD
> +                               PCI_BDF(0, 30, 2) INTB PIRQB
> +                               PCI_BDF(0, 30, 3) INTC PIRQC
> +                               PCI_BDF(0, 30, 4) INTD PIRQD
> +                               PCI_BDF(0, 30, 5) INTB PIRQB
> +                               PCI_BDF(0, 31, 3) INTB PIRQB
> +
> +                               /* PCIe root ports downstream interrupts */
> +                               PCI_BDF(1, 0, 0) INTA PIRQA
> +                               PCI_BDF(1, 0, 0) INTB PIRQB
> +                               PCI_BDF(1, 0, 0) INTC PIRQC
> +                               PCI_BDF(1, 0, 0) INTD PIRQD
> +                               PCI_BDF(2, 0, 0) INTA PIRQB
> +                               PCI_BDF(2, 0, 0) INTB PIRQC
> +                               PCI_BDF(2, 0, 0) INTC PIRQD
> +                               PCI_BDF(2, 0, 0) INTD PIRQA
> +                               PCI_BDF(3, 0, 0) INTA PIRQC
> +                               PCI_BDF(3, 0, 0) INTB PIRQD
> +                               PCI_BDF(3, 0, 0) INTC PIRQA
> +                               PCI_BDF(3, 0, 0) INTD PIRQB
> +                               PCI_BDF(4, 0, 0) INTA PIRQD
> +                               PCI_BDF(4, 0, 0) INTB PIRQA
> +                               PCI_BDF(4, 0, 0) INTC PIRQB
> +                               PCI_BDF(4, 0, 0) INTD PIRQC
> +                       >;
> +               };
>         };
>
>         fsp {
> diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig
> index 578fcce..f3cf91b 100644
> --- a/configs/minnowmax_defconfig
> +++ b/configs/minnowmax_defconfig
> @@ -5,7 +5,8 @@ CONFIG_TARGET_MINNOWMAX=y
>  CONFIG_HAVE_INTEL_ME=y
>  CONFIG_SMP=y
>  CONFIG_HAVE_VGA_BIOS=y
> -CONFIG_GENERATE_SFI_TABLE=y
> +CONFIG_GENERATE_PIRQ_TABLE=y
> +CONFIG_GENERATE_MP_TABLE=y
>  CONFIG_CMD_CPU=y
>  # CONFIG_CMD_IMLS is not set
>  # CONFIG_CMD_FLASH is not set
> diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
> index 64fa676..aeb04b9 100644
> --- a/include/configs/minnowmax.h
> +++ b/include/configs/minnowmax.h
> @@ -15,6 +15,7 @@
>
>  #define CONFIG_SYS_MONITOR_LEN         (1 << 20)
>  #define CONFIG_ARCH_EARLY_INIT_R
> +#define CONFIG_ARCH_MISC_INIT
>
>  #define CONFIG_SMSC_LPC47M
>
> --

Reviewed-by: Bin Meng <bmeng.cn at gmail.com>


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