[U-Boot] [PATCH 4/9] imx: mx6: ddr add dram io configuration and header file for i.MX6SL
Peng Fan
Peng.Fan at freescale.com
Mon Aug 17 05:29:21 CEST 2015
Define two structure mx6sl_iomux_ddr_regs and mx6sl_iomux_grp_regs.
Add a new function mx6sl_dram_iocfg to configure dram io.
Add header file to define macros for register address.
Signed-off-by: Peng Fan <Peng.Fan at freescale.com>
Cc: Stefano Babic <sbabic at denx.de>
---
arch/arm/cpu/armv7/mx6/ddr.c | 55 +++++++++++++++++++++++++++++++
arch/arm/include/asm/arch-mx6/mx6-ddr.h | 50 ++++++++++++++++++++++++++++
arch/arm/include/asm/arch-mx6/mx6sl-ddr.h | 45 +++++++++++++++++++++++++
3 files changed, 150 insertions(+)
create mode 100644 arch/arm/include/asm/arch-mx6/mx6sl-ddr.h
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index 3ec3e79..3f23abf 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -115,6 +115,61 @@ void mx6ul_dram_iocfg(unsigned width,
}
#endif
+#if defined(CONFIG_MX6SL)
+void mx6sl_dram_iocfg(unsigned width,
+ const struct mx6sl_iomux_ddr_regs *ddr,
+ const struct mx6sl_iomux_grp_regs *grp)
+{
+ struct mx6sl_iomux_ddr_regs *mx6_ddr_iomux;
+ struct mx6sl_iomux_grp_regs *mx6_grp_iomux;
+
+ mx6_ddr_iomux = (struct mx6sl_iomux_ddr_regs *)MX6SL_IOM_DDR_BASE;
+ mx6_grp_iomux = (struct mx6sl_iomux_grp_regs *)MX6SL_IOM_GRP_BASE;
+
+ /* DDR IO TYPE */
+ mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
+ mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
+
+ /* CLOCK */
+ mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
+
+ /* ADDRESS */
+ mx6_ddr_iomux->dram_cas = ddr->dram_cas;
+ mx6_ddr_iomux->dram_ras = ddr->dram_ras;
+ mx6_grp_iomux->grp_addds = grp->grp_addds;
+
+ /* Control */
+ mx6_ddr_iomux->dram_reset = ddr->dram_reset;
+ mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
+ mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
+
+ /* Data Strobes */
+ mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
+ mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
+ mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
+ if (width >= 32) {
+ mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
+ mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
+ }
+
+ /* Data */
+ mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
+ mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
+ mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
+ if (width >= 32) {
+ mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
+ mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
+ }
+
+ mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
+ mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
+ if (width >= 32) {
+ mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
+ mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
+ }
+}
+#endif
+
#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
/* Configure MX6DQ mmdc iomux */
void mx6dq_dram_iocfg(unsigned width,
diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
index f3194da..235a44a 100644
--- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
@@ -19,7 +19,11 @@
#ifdef CONFIG_MX6UL
#include "mx6ul-ddr.h"
#else
+#ifdef CONFIG_MX6SL
+#include "mx6sl-ddr.h"
+#else
#error "Please select cpu"
+#endif /* CONFIG_MX6SL */
#endif /* CONFIG_MX6UL */
#endif /* CONFIG_MX6SX */
#endif /* CONFIG_MX6DL or CONFIG_MX6S */
@@ -113,6 +117,49 @@ struct mmdc_p_regs {
u32 mpdccr;
};
+#define MX6SL_IOM_DDR_BASE 0x020e0300
+struct mx6sl_iomux_ddr_regs {
+ u32 dram_cas;
+ u32 dram_cs0_b;
+ u32 dram_cs1_b;
+ u32 dram_dqm0;
+ u32 dram_dqm1;
+ u32 dram_dqm2;
+ u32 dram_dqm3;
+ u32 dram_ras;
+ u32 dram_reset;
+ u32 dram_sdba0;
+ u32 dram_sdba1;
+ u32 dram_sdba2;
+ u32 dram_sdcke0;
+ u32 dram_sdcke1;
+ u32 dram_sdclk_0;
+ u32 dram_odt0;
+ u32 dram_odt1;
+ u32 dram_sdqs0;
+ u32 dram_sdqs1;
+ u32 dram_sdqs2;
+ u32 dram_sdqs3;
+ u32 dram_sdwe_b;
+};
+
+#define MX6SL_IOM_GRP_BASE 0x020e0500
+struct mx6sl_iomux_grp_regs {
+ u32 res1[43];
+ u32 grp_addds;
+ u32 grp_ddrmode_ctl;
+ u32 grp_ddrpke;
+ u32 grp_ddrpk;
+ u32 grp_ddrhys;
+ u32 grp_ddrmode;
+ u32 grp_b0ds;
+ u32 grp_ctlds;
+ u32 grp_b1ds;
+ u32 grp_ddr_type;
+ u32 grp_b2ds;
+ u32 grp_b3ds;
+};
+
#define MX6UL_IOM_DDR_BASE 0x020e0200
struct mx6ul_iomux_ddr_regs {
u32 res1[17];
@@ -382,6 +429,9 @@ void mx6sx_dram_iocfg(unsigned width,
void mx6ul_dram_iocfg(unsigned width,
const struct mx6ul_iomux_ddr_regs *,
const struct mx6ul_iomux_grp_regs *);
+void mx6sl_dram_iocfg(unsigned width,
+ const struct mx6sl_iomux_ddr_regs *,
+ const struct mx6sl_iomux_grp_regs *);
/* configure mx6 mmdc registers */
void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,
diff --git a/arch/arm/include/asm/arch-mx6/mx6sl-ddr.h b/arch/arm/include/asm/arch-mx6/mx6sl-ddr.h
new file mode 100644
index 0000000..c3c4d69
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6sl-ddr.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MX6SL_DDR_H__
+#define __ASM_ARCH_MX6SL_DDR_H__
+
+#ifndef CONFIG_MX6SL
+#error "wrong CPU"
+#endif
+
+#define MX6_IOM_DRAM_CAS_B 0x020e0300
+#define MX6_IOM_DRAM_CS0_B 0x020e0304
+#define MX6_IOM_DRAM_CS1_B 0x020e0308
+
+#define MX6_IOM_DRAM_DQM0 0x020e030c
+#define MX6_IOM_DRAM_DQM1 0x020e0310
+#define MX6_IOM_DRAM_DQM2 0x020e0314
+#define MX6_IOM_DRAM_DQM3 0x020e0318
+
+#define MX6_IOM_DRAM_RAS_B 0x020e031c
+#define MX6_IOM_DRAM_RESET 0x020e0320
+
+#define MX6_IOM_DRAM_SDBA0 0x020e0324
+#define MX6_IOM_DRAM_SDBA1 0x020e0328
+#define MX6_IOM_DRAM_SDBA2 0x020e032c
+
+#define MX6_IOM_DRAM_SDCKE0 0x020e0330
+#define MX6_IOM_DRAM_SDCKE1 0x020e0334
+
+#define MX6_IOM_DRAM_SDCLK0_P 0x020e0338
+
+#define MX6_IOM_DRAM_ODT0 0x020e033c
+#define MX6_IOM_DRAM_ODT1 0x020e0340
+
+#define MX6_IOM_DRAM_SDQS0_P 0x020e0344
+#define MX6_IOM_DRAM_SDQS1_P 0x020e0348
+#define MX6_IOM_DRAM_SDQS2_P 0x020e034c
+#define MX6_IOM_DRAM_SDQS3_P 0x020e0350
+
+#define MX6_IOM_DRAM_SDWE_B 0x020e0354
+
+#endif /*__ASM_ARCH_MX6SL_DDR_H__ */
--
1.8.4
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