[U-Boot] [PATCH v2 8/9] WIP: x86: gpio: Handle the case where reading a GPIO fails

[Simon Glass]

It should be possible to read an output GPIO. For now it is not clear
how to do this. Perhaps the driver should be adjusted to use memory-mapped
access throughout. For now, return an error to avoid confusion.

Not to apply.

Signed-off-by: Simon Glass <sjg at chromium.org>
---

Changes in v2: None

 drivers/gpio/intel_ich6_gpio.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index 67bf0a2..5cc86d7 100644
--- a/drivers/gpio/intel_ich6_gpio.c
+++ b/drivers/gpio/intel_ich6_gpio.c
@@ -195,6 +195,14 @@ static int _ich6_gpio_set_direction(uint16_t base, unsigned offset, int dir)
 	return 0;
 }
 
+static int _ich6_gpio_get_direction(uint16_t base, unsigned offset)
+{
+	u32 val;
+
+	val = inl(base);
+	return !(val & (1UL << offset));
+}
+
 static int _gpio_ich6_pinctrl_cfg_pin(s32 gpiobase, s32 iobase, int pin_node)
 {
 	u32 gpio_offset[2];
@@ -432,6 +440,13 @@ static int ich6_gpio_get_value(struct udevice *dev, unsigned offset)
 	u32 tmplong;
 	int r;
 
+	/*
+	 * TODO: Mirror this register since reading only works when it is an
+	 * input, Alternatively figure out how to make the hardware work with
+	 * this.
+	 */
+	if (_ich6_gpio_get_direction(bank->io_sel, offset))
+		return -EIO;
 	tmplong = inl(bank->lvl);
 	r = (tmplong & (1UL << offset)) ? 1 : 0;
 	return r;
-- 
2.5.0.457.gab17608