[U-Boot] [PATCH 0/3] arm: tegra20/colibri_t20: early pmic rail configuration

[Marcel Ziswiler]

On 24 Aug 2015 18:25, Stephen Warren <swarren at wwwdotorg.org> wrote:

> That almost sounds like there's no need for this patch/series then,
> since we're assuming that SW won't leave the HW in a bad state.

Well, define bad state please.

> If SW
> can leave HW in a bad state, the only choice is to fix the issue in HW.

As mentioned before I don't quite agree.

> However, perhaps you mean there are some states that are worse than
> others; we assume that the rails required for the AVP are always in a
> good state but the rails required for the CPU/CCPLEX may not be?

No, at the end I'm just talking about regular DVFS operation. In fact the AVPs rail gets adjusted too however not in any way such that it won't operate any longer.