[U-Boot] [PATCH v5 0/5] spi: cadence_qspi: optimize & fix indirect rd-writes

[Vikas Manocha]

This patchset:
- fixes trigger base & transfer start address register programming. This fix
superseeds the previous patch "spi: cadence_qspi: Fix the indirect ahb trigger
address setting".
- adds support to get fifo width from device tree

Changes in v5:
- fixed compilation warnings.

Changes in v4:
- fifo-width & trigger address alligned to linux device tree binding.
- removed un-necessary casting.
- renaming of one parameter splitted to separate patch.
- trigger address of socfpga reverted back to 0x0.
- code formatting done to avoid checkpatch CHECKS.

Changes in v3:
- removed two patches which were bypassing the sram level check.
- format string in patch corrected 3/4
- added commit message in patch 1/4

Changes in v2:
- rebased to master.
- removed patch "spi: cadence_qspi: read can be independent of fifo width", it
  was implemented in other patchset, in mainline now.

Vikas Manocha (5):
  spi: cadence_qspi: move trigger base configuration in init
  spi: cadence_qspi: fix indirect read/write start address
  spi: cadence_qspi: fix base trigger address & transfer start address
  spi: cadence_qspi: rename ahbbase to flashbase for clarity
  spi: cadence_qspi: get fifo width from device tree

 arch/arm/dts/socfpga.dtsi      |    2 ++
 arch/arm/dts/stv0991.dts       |    2 ++
 drivers/spi/cadence_qspi.c     |   14 ++++++++------
 drivers/spi/cadence_qspi.h     |    6 ++++--
 drivers/spi/cadence_qspi_apb.c |   42 ++++++++++++++++------------------------
 5 files changed, 33 insertions(+), 33 deletions(-)

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1.7.9.5