[U-Boot] [PATCH v5 1/5] spi: cadence_qspi: move trigger base configuration in init

[Marek Vasut]

On Thursday, August 27, 2015 at 12:44:26 AM, Vikas Manocha wrote:
> No need to configure indirect trigger address for every read/write.
> 
> Signed-off-by: Vikas Manocha <vikas.manocha at st.com>
> ---
> 
> Changes in v5: fixed type cast compilation warnings.
> Changes in v4: removed extra type casts.
> Changes in v3: added commit message & removed extra bracket.
> Changes in v2: Rebased to master
> 
>  drivers/spi/cadence_qspi_apb.c |    9 ++-------
>  1 file changed, 2 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/spi/cadence_qspi_apb.c
> b/drivers/spi/cadence_qspi_apb.c index d053407..d377ad1 100644
> --- a/drivers/spi/cadence_qspi_apb.c
> +++ b/drivers/spi/cadence_qspi_apb.c
> @@ -534,6 +534,8 @@ void cadence_qspi_apb_controller_init(struct
> cadence_spi_platdata *plat)
> 
>  	/* Indirect mode configurations */
>  	writel((plat->sram_size/2), plat->regbase + CQSPI_REG_SRAMPARTITION);
> +	writel((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK,

Why can't you just drop this masking and the cast ?

> +	       plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
> 
>  	/* Disable all interrupts */
>  	writel(0, plat->regbase + CQSPI_REG_IRQMASK);

[...]

Best regards,
Marek Vasut