[U-Boot] [PATCH v5 2/5] spi: cadence_qspi: fix indirect read/write start address

[Vikas MANOCHA]

Hi,

> -----Original Message-----
> From: Marek Vasut [mailto:marex at denx.de]
> Sent: Thursday, August 27, 2015 1:38 AM
> To: Vikas MANOCHA
> Cc: u-boot at lists.denx.de; sr at denx.de; grmoore at opensource.altera.com;
> jteki at openedev.com
> Subject: Re: [PATCH v5 2/5] spi: cadence_qspi: fix indirect read/write start
> address
> 
> On Thursday, August 27, 2015 at 12:44:27 AM, Vikas Manocha wrote:
> > Indirect read/write start addresses are flash start addresses for
> > indirect read or write transfers. These should be absolute flash
> > addresses instead of offsets.
> 
> Can you elaborate on this "flash address" thing you keep flinging around?
> What does that mean exactly ? This is very ambiguous thing.

It's not rocket science, study this  link & you will stop wondering (esp first line of "NOR memories"):
https://en.wikipedia.org/wiki/Flash_memory

> 
> > Signed-off-by: Vikas Manocha <vikas.manocha at st.com>
> > ---
> >
> > Changes in v5: fixed type cast compilation warnings.
> > Changes in v4: removed extra type casts.
> > Changes in v3: none
> > Changes in v2: Rebased to master
> >
> >  drivers/spi/cadence_qspi_apb.c |    6 ++++--
> >  1 file changed, 4 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/spi/cadence_qspi_apb.c
> > b/drivers/spi/cadence_qspi_apb.c index d377ad1..c5b14c5 100644
> > --- a/drivers/spi/cadence_qspi_apb.c
> > +++ b/drivers/spi/cadence_qspi_apb.c
> > @@ -705,7 +705,8 @@ int cadence_qspi_apb_indirect_read_setup(struct
> > cadence_spi_platdata *plat,
> >
> >  	/* Get address */
> >  	addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1],
> addr_bytes);
> > -	writel(addr_value, plat->regbase +
> CQSPI_REG_INDIRECTRDSTARTADDR);
> > +	writel((u32)plat->ahbbase + addr_value,
> 
> The cast is not needed.

Again, cast is required as ahbbase is pointer. 

> 
> > +	       plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
> >
> >  	/* The remaining lenght is dummy bytes. */
> >  	dummy_bytes = cmdlen - addr_bytes - 1; @@ -795,7 +796,8 @@ int
> > cadence_qspi_apb_indirect_write_setup(struct
> > cadence_spi_platdata *plat,
> >
> >  	/* Setup write address. */
> >  	reg = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
> > -	writel(reg, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
> > +	writel((u32)plat->ahbbase + reg,
> 
> DTTO

Read above.

Cheers,
Vikas

> 
> > +	       plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
> >
> >  	reg = readl(plat->regbase + CQSPI_REG_SIZE);
> >  	reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
> 
> Best regards,
> Marek Vasut