[U-Boot] ls2085ardb not booting

[Scott Wood]

I'm unable to boot ls2085ardb on the current tree.  I get no console output.  
v2015.07 gives some output, but hangs at:

> U-Boot 2015.07 (Aug 27 2015 - 16:24:43 -0500) LS2085A-RDB

> 

> Clock Configuration:
>        CPU0(A57):1600 MHz  CPU1(A57):1600 MHz  CPU2(A57):1600 MHz  
>        CPU3(A57):1600 MHz  CPU4(A57):1600 MHz  CPU5(A57):1600 MHz  
>        CPU6(A57):1600 MHz  CPU7(A57):1600 MHz  
>        Bus:      600  MHz  DDR:      1333.333 MHz     DP-DDR:   1333.333 MHz
> Reset Configuration Word (RCW):
>        00: 40282830 40400040 00000000 00000000
>        10: 00000000 00200000 00200000 00000000
>        20: 00c12980 00002580 00000000 00000000
>        30: 00000e0b 00000000 00000000 00000000
>        40: 00000000 00000000 00000000 00000000
>        50: 00000000 00000000 00000000 00000000
>        60: 00000000 00000000 00027000 00000000
>        70: 412a0000 00000000 00000000 00000000
> Board:  LS2085A-RDB, Board Arch: V1, Board version: C, boot from vBank: 4
> FPGA: v1.18
> SERDES1 Reference : Clock1 = 156.25MHz Clock2 = 156.25MHz
> SERDES2 Reference : Clock1 = 100MHz Clock2 = 100MHz
> I2C:   ready
> DRAM:  Initializing DDR....using SPD
> Detected UDIMM 18ASF1G72AZ-2G1A1 
> Detected UDIMM 18ASF1G72AZ-2G1A1 
> There is no rank on CS0 for controller 1.
> Controler 1 timeout, debug_2 = 2100
> Controler 1 timeout, debug_2 = 2500
> Waiting for D_INIT timeout. Memory may not work.
> DP-DDR:  Detected UDIMM 18ASF1G72AZ-2G1A1 
> 19.5 GiB
> DDR    15.5 GiB (DDR4, 64-bit, CL=9, ECC on)
>        DDR Chip-Select Interleaving Mode: CS0+CS1
> DP-DDR 4 GiB (DDR4, 32-bit, CL=9, ECC on)
>        DDR Chip-Select Interleaving Mode: CS0+CS1
The internal bringup branch does boot on the same board, with the same RCW.

-Scott