[U-Boot] [PATCH v5 27/41] rockchip: Add core SoC start-up code
Simon Glass
sjg at chromium.org
Mon Aug 31 00:55:38 CEST 2015
Add code for starting up U-Boot SPL and U-Boot proper. This is generic and
makes use of devices provided by the board- or SoC-specific code.
Signed-off-by: Simon Glass <sjg at chromium.org>
---
Changes in v5:
- Drop BSS memset() as it is not needed
- Use CONFIG_SPL_LED instead of CONFIG_SPL_LED_SUPPORT
Changes in v4:
- Rename pinctrl.h to dm/pinctrl.h
Changes in v3: None
Changes in v2: None
arch/arm/Kconfig | 10 ++
arch/arm/Makefile | 1 +
arch/arm/mach-rockchip/Kconfig | 41 +++++
arch/arm/mach-rockchip/Makefile | 13 ++
arch/arm/mach-rockchip/board-spl.c | 287 ++++++++++++++++++++++++++++++++++
arch/arm/mach-rockchip/board.c | 46 ++++++
arch/arm/mach-rockchip/common.c | 28 ++++
arch/arm/mach-rockchip/rk3288/Kconfig | 6 +
8 files changed, 432 insertions(+)
create mode 100644 arch/arm/mach-rockchip/Kconfig
create mode 100644 arch/arm/mach-rockchip/Makefile
create mode 100644 arch/arm/mach-rockchip/board-spl.c
create mode 100644 arch/arm/mach-rockchip/board.c
create mode 100644 arch/arm/mach-rockchip/common.c
create mode 100644 arch/arm/mach-rockchip/rk3288/Kconfig
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a99ae28..1f2eccd 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -827,6 +827,14 @@ config TARGET_STM32F429_DISCOVERY
bool "Support STM32F429 Discovery"
select CPU_V7M
+config ARCH_ROCKCHIP
+ bool "Support Rockchip SoCs"
+ select SUPPORT_SPL
+ select SPL
+ select OF_CONTROL
+ select CPU_V7
+ select DM
+
endchoice
source "arch/arm/mach-at91/Kconfig"
@@ -861,6 +869,8 @@ source "arch/arm/mach-orion5x/Kconfig"
source "arch/arm/cpu/armv7/rmobile/Kconfig"
+source "arch/arm/mach-rockchip/Kconfig"
+
source "arch/arm/cpu/armv7/s5pc1xx/Kconfig"
source "arch/arm/mach-socfpga/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index e84d6d3..1eca815 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -55,6 +55,7 @@ machine-$(CONFIG_ARCH_NOMADIK) += nomadik
# TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
machine-$(CONFIG_ORION5X) += orion5x
machine-$(CONFIG_ARCH_SOCFPGA) += socfpga
+machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip
machine-$(CONFIG_TEGRA) += tegra
machine-$(CONFIG_ARCH_UNIPHIER) += uniphier
machine-$(CONFIG_ARCH_VERSATILE) += versatile
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
new file mode 100644
index 0000000..ab50f4e
--- /dev/null
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -0,0 +1,41 @@
+if ARCH_ROCKCHIP
+
+config ROCKCHIP_RK3288
+ bool "Support Rockchip RK3288"
+ help
+ The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
+ including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
+ video interfaces supporting HDMI and eDP, several DDR3 options
+ and video codec support. Peripherals include Gigabit Ethernet,
+ USB2 host and OTG, SDIO, I2S, UART,s, SPI, I2C and PWMs.
+
+config SYS_MALLOC_F
+ default y
+
+config SYS_MALLOC_F_LEN
+ default 0x800
+
+config SPL_DM
+ default y
+
+config DM_SERIAL
+ default y
+
+config DM_SPI
+ default y
+
+config DM_SPI_FLASH
+ default y
+
+config DM_I2C
+ default y
+
+config DM_GPIO
+ default y
+
+config ROCKCHIP_SERIAL
+ default y
+
+source "arch/arm/mach-rockchip/rk3288/Kconfig"
+
+endif
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
new file mode 100644
index 0000000..5a4e383
--- /dev/null
+++ b/arch/arm/mach-rockchip/Makefile
@@ -0,0 +1,13 @@
+#
+# Copyright (c) 2014 Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y += board-spl.o
+else
+obj-y += board.o
+endif
+obj-y += common.o
+obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
diff --git a/arch/arm/mach-rockchip/board-spl.c b/arch/arm/mach-rockchip/board-spl.c
new file mode 100644
index 0000000..a241d96
--- /dev/null
+++ b/arch/arm/mach-rockchip/board-spl.c
@@ -0,0 +1,287 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <led.h>
+#include <malloc.h>
+#include <ram.h>
+#include <spl.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/sdram.h>
+#include <dm/pinctrl.h>
+#include <dm/root.h>
+#include <dm/test.h>
+#include <dm/util.h>
+#include <power/regulator.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 spl_boot_device(void)
+{
+ const void *blob = gd->fdt_blob;
+ struct udevice *dev;
+ const char *bootdev;
+ int node;
+ int ret;
+
+ bootdev = fdtdec_get_config_string(blob, "u-boot,boot0");
+ debug("Boot device %s\n", bootdev);
+ if (!bootdev)
+ goto fallback;
+
+ node = fdt_path_offset(blob, bootdev);
+ if (node < 0) {
+ debug("node=%d\n", node);
+ goto fallback;
+ }
+ ret = device_get_global_by_of_offset(node, &dev);
+ if (ret) {
+ debug("device at node %s/%d not found: %d\n", bootdev, node,
+ ret);
+ goto fallback;
+ }
+ debug("Found device %s\n", dev->name);
+ switch (device_get_uclass_id(dev)) {
+ case UCLASS_SPI_FLASH:
+ return BOOT_DEVICE_SPI;
+ case UCLASS_MMC:
+ return BOOT_DEVICE_MMC1;
+ default:
+ debug("Booting from device uclass '%s' not supported\n",
+ dev_get_uclass_name(dev));
+ }
+
+fallback:
+ return BOOT_DEVICE_MMC1;
+}
+
+u32 spl_boot_mode(void)
+{
+ return MMCSD_MODE_RAW;
+}
+
+/* read L2 control register (L2CTLR) */
+static inline uint32_t read_l2ctlr(void)
+{
+ uint32_t val = 0;
+
+ asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
+
+ return val;
+}
+
+/* write L2 control register (L2CTLR) */
+static inline void write_l2ctlr(uint32_t val)
+{
+ /*
+ * Note: L2CTLR can only be written when the L2 memory system
+ * is idle, ie before the MMU is enabled.
+ */
+ asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory");
+ isb();
+}
+
+static void configure_l2ctlr(void)
+{
+ uint32_t l2ctlr;
+
+ l2ctlr = read_l2ctlr();
+ l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
+
+ /*
+ * Data RAM write latency: 2 cycles
+ * Data RAM read latency: 2 cycles
+ * Data RAM setup latency: 1 cycle
+ * Tag RAM write latency: 1 cycle
+ * Tag RAM read latency: 1 cycle
+ * Tag RAM setup latency: 1 cycle
+ */
+ l2ctlr |= (1 << 3 | 1 << 0);
+ write_l2ctlr(l2ctlr);
+}
+
+struct rk3288_timer {
+ u32 timer_load_count0;
+ u32 timer_load_count1;
+ u32 timer_curr_value0;
+ u32 timer_curr_value1;
+ u32 timer_ctrl_reg;
+ u32 timer_int_status;
+};
+
+void init_timer(void)
+{
+ struct rk3288_timer * const timer7_ptr = (void *)TIMER7_BASE;
+
+ writel(0xffffffff, &timer7_ptr->timer_load_count0);
+ writel(0xffffffff, &timer7_ptr->timer_load_count1);
+ writel(1, &timer7_ptr->timer_ctrl_reg);
+}
+
+static int configure_emmc(struct udevice *pinctrl)
+{
+ struct gpio_desc desc;
+ int ret;
+
+ pinctrl_request_noflags(pinctrl, PERIPH_ID_EMMC);
+
+ /*
+ * TODO(sjg at chromium.org): Pick this up from device tree or perhaps
+ * use the EMMC_PWREN setting.
+ */
+ ret = dm_gpio_lookup_name("D9", &desc);
+ if (ret) {
+ debug("gpio ret=%d\n", ret);
+ return ret;
+ }
+ ret = dm_gpio_request(&desc, "emmc_pwren");
+ if (ret) {
+ debug("gpio_request ret=%d\n", ret);
+ return ret;
+ }
+ ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
+ if (ret) {
+ debug("gpio dir ret=%d\n", ret);
+ return ret;
+ }
+ ret = dm_gpio_set_value(&desc, 1);
+ if (ret) {
+ debug("gpio value ret=%d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+ struct udevice *pinctrl;
+ struct udevice *dev;
+ int ret;
+
+ /* Example code showing how to enable the debug UART on RK3288 */
+#ifdef EARLY_UART
+#include <asm/arch/grf_rk3288.h>
+ /* Enable early UART on the RK3288 */
+#define GRF_BASE 0xff770000
+ struct rk3288_grf * const grf = (void *)GRF_BASE;
+
+ rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT |
+ GPIO7C6_MASK << GPIO7C6_SHIFT,
+ GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
+ GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
+ /*
+ * Debug UART can be used from here if required:
+ *
+ * debug_uart_init();
+ * printch('a');
+ * printhex8(0x1234);
+ * printascii("string");
+ */
+ debug_uart_init();
+#endif
+
+ ret = spl_init();
+ if (ret) {
+ debug("spl_init() failed: %d\n", ret);
+ hang();
+ }
+
+ init_timer();
+ configure_l2ctlr();
+
+ ret = uclass_get_device(UCLASS_CLK, 0, &dev);
+ if (ret) {
+ debug("CLK init failed: %d\n", ret);
+ return;
+ }
+
+ ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
+ if (ret) {
+ debug("Pinctrl init failed: %d\n", ret);
+ return;
+ }
+
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ debug("DRAM init failed: %d\n", ret);
+ return;
+ }
+}
+
+static int setup_led(void)
+{
+#ifdef CONFIG_SPL_LED
+ struct udevice *dev;
+ char *led_name;
+ int ret;
+
+ led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
+ if (!led_name)
+ return 0;
+ ret = led_get_by_label(led_name, &dev);
+ if (ret) {
+ debug("%s: get=%d\n", __func__, ret);
+ return ret;
+ }
+ ret = led_set_on(dev, 1);
+ if (ret)
+ return ret;
+#endif
+
+ return 0;
+}
+
+void spl_board_init(void)
+{
+ struct udevice *pinctrl;
+ int ret;
+
+ ret = setup_led();
+
+ if (ret) {
+ debug("LED ret=%d\n", ret);
+ hang();
+ }
+
+ ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
+ if (ret) {
+ debug("%s: Cannot find pinctrl device\n", __func__);
+ goto err;
+ }
+ ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
+ if (ret) {
+ debug("%s: Failed to set up SD card\n", __func__);
+ goto err;
+ }
+ ret = configure_emmc(pinctrl);
+ if (ret) {
+ debug("%s: Failed to set up eMMC\n", __func__);
+ goto err;
+ }
+
+ /* Enable debug UART */
+ ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
+ if (ret) {
+ debug("%s: Failed to set up console UART\n", __func__);
+ goto err;
+ }
+
+ preloader_console_init();
+ return;
+err:
+ printf("spl_board_init: Error %d\n", ret);
+
+ /* No way to report error here */
+ hang();
+}
diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
new file mode 100644
index 0000000..688bc0f
--- /dev/null
+++ b/arch/arm/mach-rockchip/board.c
@@ -0,0 +1,46 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <ram.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ struct ram_info ram;
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ debug("DRAM init failed: %d\n", ret);
+ return ret;
+ }
+ ret = ram_get_info(dev, &ram);
+ if (ret) {
+ debug("Cannot get DRAM size: %d\n", ret);
+ return ret;
+ }
+ debug("SDRAM base=%lx, size=%x\n", ram.base, ram.size);
+ gd->ram_size = ram.size;
+
+ return 0;
+}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+}
+#endif
diff --git a/arch/arm/mach-rockchip/common.c b/arch/arm/mach-rockchip/common.c
new file mode 100644
index 0000000..fc7ac72
--- /dev/null
+++ b/arch/arm/mach-rockchip/common.c
@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <linux/err.h>
+
+void *rockchip_get_cru(void)
+{
+ struct udevice *dev;
+ fdt_addr_t addr;
+ int ret;
+
+ ret = uclass_get_device(UCLASS_CLK, 0, &dev);
+ if (ret)
+ return ERR_PTR(ret);
+
+ addr = dev_get_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return ERR_PTR(-EINVAL);
+
+ return (void *)addr;
+}
diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig
new file mode 100644
index 0000000..26d5951
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3288/Kconfig
@@ -0,0 +1,6 @@
+if ROCKCHIP_RK3288
+
+config SYS_SOC
+ default "rockchip"
+
+endif
--
2.5.0.457.gab17608
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