[U-Boot] [PATCH][v6] imx: mx7dsabresd: Add support for MX7D SABRESD board
Stefano Babic
sbabic at denx.de
Mon Aug 31 18:27:39 CEST 2015
Hi Adrian,
On 29/08/2015 01:08, Adrian Alonso wrote:
> * Add i.MX7D SABRESD target board support with enabled modules:
> UART, PMIC, USB/OTG, SD, eMMC, ENET, I2C, 74LV IOX.
>
> Build target: mx7dsabresd_config
>
> Signed-off-by: Peng Fan <Peng.Fan at freescale.com>
> Signed-off-by: Fugang Duan <B38611 at freescale.com>
> Signed-off-by: Ye.Li <B37916 at freescale.com>
> Signed-off-by: Adrian Alonso <aalonso at freescale.com>
> ---
> Changes for V2:
> - Include arch/arm/Kconfig target config option
> Changes for V3:
> - Update target board maintainer contact info
> Changes for V4: depends on patchs
> - mmc: fsl_esdhc invalidate dcache before read
> - imx: usb: ehci-mx6: add usb support for imx7d soc
> Changes for V5: depends on patchs
> - imx: usb: ehci-mx6: reg accessor cleanups
> - imx: usb: ehci-mx6: document board specific functions
> - imx: usb: ehci-mx6: wait_for_bit to check reg status
> Changes for V6:
> - Remove unused macro CONFIG_BOARD_POSTCLK_INIT from mc7_common.h
> - Depends on patchs:
> - arm: imx-common: init: rework wdog settings for imx6/imx7
> - arm: imx-common: init: extend init_aips to support imx7
> - arm: imx: imx-common: init: move arch init common setup
> - arm: imx: common rework cache settings for imx6
> - thermal: imx_thermal: rework driver to be reused
> - thermal: imx: add imx7d soc thermal support
>
> arch/arm/Kconfig | 7 +
> board/freescale/mx7dsabresd/Kconfig | 15 +
> board/freescale/mx7dsabresd/MAINTAINERS | 6 +
> board/freescale/mx7dsabresd/Makefile | 6 +
> board/freescale/mx7dsabresd/imximage.cfg | 103 +++++
> board/freescale/mx7dsabresd/mx7dsabresd.c | 642 ++++++++++++++++++++++++++++++
> configs/mx7dsabresd_defconfig | 10 +
> include/configs/mx7_common.h | 21 +
> include/configs/mx7dsabresd.h | 355 +++++++++++++++++
> 9 files changed, 1165 insertions(+)
> create mode 100644 board/freescale/mx7dsabresd/Kconfig
> create mode 100644 board/freescale/mx7dsabresd/MAINTAINERS
> create mode 100644 board/freescale/mx7dsabresd/Makefile
> create mode 100644 board/freescale/mx7dsabresd/imximage.cfg
> create mode 100644 board/freescale/mx7dsabresd/mx7dsabresd.c
> create mode 100644 configs/mx7dsabresd_defconfig
> create mode 100644 include/configs/mx7_common.h
> create mode 100644 include/configs/mx7dsabresd.h
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index a99ae28..416c784 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -588,6 +588,12 @@ config TARGET_MX6UL_14X14_EVK
> select DM_THERMAL
> select SUPPORT_SPL
>
> +config TARGET_MX7DSABRESD
> + bool "Support mx7dsabresd"
> + select CPU_V7
> + select DM
> + select DM_THERMAL
> +
> config TARGET_GW_VENTANA
> bool "Support gw_ventana"
> select CPU_V7
> @@ -935,6 +941,7 @@ source "board/freescale/mx6sabresd/Kconfig"
> source "board/freescale/mx6slevk/Kconfig"
> source "board/freescale/mx6sxsabresd/Kconfig"
> source "board/freescale/mx6ul_14x14_evk/Kconfig"
> +source "board/freescale/mx7dsabresd/Kconfig"
> source "board/freescale/vf610twr/Kconfig"
> source "board/gateworks/gw_ventana/Kconfig"
> source "board/genesi/mx51_efikamx/Kconfig"
> diff --git a/board/freescale/mx7dsabresd/Kconfig b/board/freescale/mx7dsabresd/Kconfig
> new file mode 100644
> index 0000000..d7c6ae4
> --- /dev/null
> +++ b/board/freescale/mx7dsabresd/Kconfig
> @@ -0,0 +1,15 @@
> +if TARGET_MX7DSABRESD
> +
> +config SYS_BOARD
> + default "mx7dsabresd"
> +
> +config SYS_VENDOR
> + default "freescale"
> +
> +config SYS_SOC
> + default "mx7"
> +
> +config SYS_CONFIG_NAME
> + default "mx7dsabresd"
> +
> +endif
> diff --git a/board/freescale/mx7dsabresd/MAINTAINERS b/board/freescale/mx7dsabresd/MAINTAINERS
> new file mode 100644
> index 0000000..3910ee4
> --- /dev/null
> +++ b/board/freescale/mx7dsabresd/MAINTAINERS
> @@ -0,0 +1,6 @@
> +MX7DSABRESD BOARD
> +M: Adrian Alonso <aalonso at freescale.com>
> +S: Maintained
> +F: board/freescale/mx7dsabresd
> +F: include/configs/mx7dsabresd.h
> +F: configs/mx7dsabresd_defconfig
> diff --git a/board/freescale/mx7dsabresd/Makefile b/board/freescale/mx7dsabresd/Makefile
> new file mode 100644
> index 0000000..14336ab
> --- /dev/null
> +++ b/board/freescale/mx7dsabresd/Makefile
> @@ -0,0 +1,6 @@
> +# (C) Copyright 2015 Freescale Semiconductor, Inc.
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +obj-y := mx7dsabresd.o
> diff --git a/board/freescale/mx7dsabresd/imximage.cfg b/board/freescale/mx7dsabresd/imximage.cfg
> new file mode 100644
> index 0000000..5088d0e
> --- /dev/null
> +++ b/board/freescale/mx7dsabresd/imximage.cfg
> @@ -0,0 +1,103 @@
> +/*
> + * Copyright (C) 2015 Freescale Semiconductor, Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + *
> + * Refer docs/README.imxmage for more details about how-to configure
> + * and create imximage boot image
> + *
> + * The syntax is taken as close as possible with the kwbimage
> + */
> +
> +#define __ASSEMBLY__
> +#include <config.h>
> +
> +/* image version */
> +
> +IMAGE_VERSION 2
> +
> +/*
> + * Boot Device : one of
> + * spi/sd/nand/onenand, qspi/nor
> + */
> +
> +#ifdef CONFIG_SYS_BOOT_QSPI
> +BOOT_FROM qspi
> +#elif defined(CONFIG_SYS_BOOT_EIMNOR)
> +BOOT_FROM nor
> +#else
> +BOOT_FROM sd
> +#endif
> +
> +#ifdef CONFIG_SECURE_BOOT
> +CSF CONFIG_CSF_SIZE
> +#endif
> +
> +/*
> + * Device Configuration Data (DCD)
> + *
> + * Each entry must have the format:
> + * Addr-type Address Value
> + *
> + * where:
> + * Addr-type register length (1,2 or 4 bytes)
> + * Address absolute address of the register
> + * value value to be stored in the register
> + */
> +
> +DATA 4 0x30340004 0x4F400005
> +
> +DATA 4 0x30391000 0x00000002
> +DATA 4 0x307a0000 0x03040001
> +DATA 4 0x307a01a0 0x80400003
> +DATA 4 0x307a01a4 0x00100020
> +DATA 4 0x307a01a8 0x80100004
> +DATA 4 0x307a0064 0x0040005e
> +DATA 4 0x307a0490 0x00000001
> +DATA 4 0x307a00d0 0x00020001
> +DATA 4 0x307a00d4 0x00010000
> +DATA 4 0x307a00dc 0x09300004
> +DATA 4 0x307a00e0 0x04080000
> +DATA 4 0x307a00e4 0x00090004
> +DATA 4 0x307a00f4 0x0000033f
> +DATA 4 0x307a0100 0x0908120a
> +DATA 4 0x307a0104 0x0002020e
> +DATA 4 0x307a0108 0x03040407
> +DATA 4 0x307a010c 0x00002006
> +DATA 4 0x307a0110 0x04020204
> +DATA 4 0x307a0114 0x03030202
> +DATA 4 0x307a0120 0x03030803
> +DATA 4 0x307a0180 0x00800020
> +DATA 4 0x307a0190 0x02098204
> +DATA 4 0x307a0194 0x00030303
> +DATA 4 0x307a0200 0x00000016
> +DATA 4 0x307a0204 0x00171717
> +DATA 4 0x307a0214 0x04040404
> +DATA 4 0x307a0218 0x00040404
> +DATA 4 0x307a0240 0x06000601
> +DATA 4 0x307a0244 0x00001323
> +DATA 4 0x30391000 0x00000000
> +DATA 4 0x30790000 0x17420f40
> +DATA 4 0x30790004 0x10210100
> +DATA 4 0x30790010 0x00060807
> +DATA 4 0x3079009c 0x00000d6e
> +DATA 4 0x30790020 0x08080808
> +DATA 4 0x30790030 0x08080808
> +DATA 4 0x30790050 0x01000010
> +DATA 4 0x30790050 0x00000010
> +
> +DATA 4 0x307900c0 0x0e407304
> +DATA 4 0x307900c0 0x0e447304
> +DATA 4 0x307900c0 0x0e447306
> +
> +CHECK_BITS_SET 4 0x307900c4 0x1
> +
> +DATA 4 0x307900c0 0x0e447304
> +DATA 4 0x307900c0 0x0e407304
> +
> +DATA 4 0x30384130 0x00000000
> +DATA 4 0x30340020 0x00000178
> +DATA 4 0x30384130 0x00000002
> +DATA 4 0x30790018 0x0000000f
> +
> +CHECK_BITS_SET 4 0x307a0004 0x1
> diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c
> new file mode 100644
> index 0000000..1d5928f
> --- /dev/null
> +++ b/board/freescale/mx7dsabresd/mx7dsabresd.c
> @@ -0,0 +1,642 @@
> +/*
> + * Copyright (C) 2015 Freescale Semiconductor, Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <asm/arch/clock.h>
> +#include <asm/arch/imx-regs.h>
> +#include <asm/arch/mx7-pins.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/gpio.h>
> +#include <asm/imx-common/iomux-v3.h>
> +#include <asm/imx-common/boot_mode.h>
> +#include <asm/io.h>
> +#include <linux/sizes.h>
> +#include <common.h>
> +#include <fsl_esdhc.h>
> +#include <mmc.h>
> +#include <miiphy.h>
> +#include <netdev.h>
> +#include <power/pmic.h>
> +#include <power/pfuze3000_pmic.h>
> +#include "../common/pfuze.h"
> +#include <i2c.h>
> +#include <asm/imx-common/mxc_i2c.h>
> +#include <asm/arch/crm_regs.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
> + PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
> +
> +#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
> + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
> +
> +#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
> +#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
> +
> +#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
> +
> +#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
> + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
> +
> +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
> + PAD_CTL_DSE_3P3V_49OHM)
> +
> +#define QSPI_PAD_CTRL \
> + (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
> +
> +#define SPI_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
> +
> +#define BUTTON_PAD_CTRL (PAD_CTL_PUS_PU5KOHM | PAD_CTL_DSE_3P3V_98OHM)
> +
> +#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
> +
> +#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
> +
> +#ifdef CONFIG_SYS_I2C_MXC
> +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
> +/* I2C1 for PMIC */
> +struct i2c_pads_info i2c_pad_info1 = {
> + .scl = {
> + .i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC,
> + .gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC,
> + .gp = IMX_GPIO_NR(4, 8),
> + },
> + .sda = {
> + .i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC,
> + .gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC,
> + .gp = IMX_GPIO_NR(4, 9),
> + },
> +};
> +#endif
> +
> +int dram_init(void)
> +{
> + gd->ram_size = PHYS_SDRAM_SIZE;
> +
> + return 0;
> +}
> +
> +static iomux_v3_cfg_t const wdog_pads[] = {
> + MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +static iomux_v3_cfg_t const uart1_pads[] = {
> + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
> + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
> +};
> +
> +static iomux_v3_cfg_t const usdhc1_pads[] = {
> + MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +
> + MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +};
> +
> +static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
> + MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +
> + MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +};
> +
> +#define IOX_SDI IMX_GPIO_NR(1, 9)
> +#define IOX_STCP IMX_GPIO_NR(1, 12)
> +#define IOX_SHCP IMX_GPIO_NR(1, 13)
> +
> +static iomux_v3_cfg_t const iox_pads[] = {
> + /* IOX_SDI */
> + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + /* IOX_STCP */
> + MX7D_PAD_GPIO1_IO12__GPIO1_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + /* IOX_SHCP */
> + MX7D_PAD_GPIO1_IO13__GPIO1_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +/*
> + * PCIE_DIS_B --> Q0
> + * PCIE_RST_B --> Q1
> + * HDMI_RST_B --> Q2
> + * PERI_RST_B --> Q3
> + * SENSOR_RST_B --> Q4
> + * ENET_RST_B --> Q5
> + * PERI_3V3_EN --> Q6
> + * LCD_PWR_EN --> Q7
> + */
> +enum qn {
> + PCIE_DIS_B,
> + PCIE_RST_B,
> + HDMI_RST_B,
> + PERI_RST_B,
> + SENSOR_RST_B,
> + ENET_RST_B,
> + PERI_3V3_EN,
> + LCD_PWR_EN,
> +};
> +
> +enum qn_func {
> + qn_reset,
> + qn_enable,
> + qn_disable,
> +};
> +
> +enum qn_level {
> + qn_low = 0,
> + qn_high = 1,
> +};
> +
> +static enum qn_level seq[3][2] = {
> + {0, 1}, {1, 1}, {0, 0}
> +};
> +
> +static enum qn_func qn_output[8] = {
> + qn_disable, qn_reset, qn_reset, qn_reset, qn_reset, qn_reset, qn_enable,
> + qn_enable
> +};
> +
> +void iox74lv_init(void)
> +{
> + int i;
> +
> + for (i = 7; i >= 0; i--) {
> + gpio_direction_output(IOX_SHCP, 0);
> + gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
> + udelay(500);
> + gpio_direction_output(IOX_SHCP, 1);
> + udelay(500);
> + }
> +
> + gpio_direction_output(IOX_STCP, 0);
> + udelay(500);
> + /*
> + * shift register will be output to pins
> + */
> + gpio_direction_output(IOX_STCP, 1);
> +
> + for (i = 7; i >= 0; i--) {
> + gpio_direction_output(IOX_SHCP, 0);
> + gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
> + udelay(500);
> + gpio_direction_output(IOX_SHCP, 1);
> + udelay(500);
> + }
> + gpio_direction_output(IOX_STCP, 0);
> + udelay(500);
> + /*
> + * shift register will be output to pins
> + */
> + gpio_direction_output(IOX_STCP, 1);
> +};
> +
> +void iox74lv_set(int index)
> +{
> + int i;
> + for (i = 7; i >= 0; i--) {
> + gpio_direction_output(IOX_SHCP, 0);
> +
> + if (i == index)
> + gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
> + else
> + gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
> + udelay(500);
> + gpio_direction_output(IOX_SHCP, 1);
> + udelay(500);
> + }
> +
> + gpio_direction_output(IOX_STCP, 0);
> + udelay(500);
> + /*
> + * shift register will be output to pins
> + */
> + gpio_direction_output(IOX_STCP, 1);
> +
> + for (i = 7; i >= 0; i--) {
> + gpio_direction_output(IOX_SHCP, 0);
> + gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
I did not know that a sequence is required for the initialization -
anyway, it is ok for me.
> + udelay(500);
> + gpio_direction_output(IOX_SHCP, 1);
> + udelay(500);
> + }
> +
> + gpio_direction_output(IOX_STCP, 0);
> + udelay(500);
> + /*
> + * shift register will be output to pins
> + */
> + gpio_direction_output(IOX_STCP, 1);
> +};
> +
> +#ifdef CONFIG_SYS_USE_NAND
> +static iomux_v3_cfg_t const gpmi_pads[] = {
> + MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
> + MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
> + MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
> + MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
> + MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
> + MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
> + MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
> + MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
> + MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
> + MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
> + MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
> + MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
> + MX7D_PAD_SAI1_MCLK__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
> + MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
> + MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
> + MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
> + MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
> + MX7D_PAD_SAI1_TX_SYNC__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL),
> + MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
> +};
> +
> +static void setup_gpmi_nand(void)
> +{
> + imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
> +
> + /*
> + * NAND_USDHC_BUS_CLK is set in rom
> + */
> +
> + set_clk_nand();
> +
> + /*
> + * APBH clock root is set in init_esdhc, USDHC3_CLK.
> + * There is no clk gate for APBHDMA.
> + * No touch here.
> + */
> +}
> +#endif
> +
> +#ifdef CONFIG_FEC_MXC
> +static iomux_v3_cfg_t const fec1_pads[] = {
> + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
> + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
> + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
> + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
> + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
> + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
> + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
> + MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
> +};
> +
> +static void setup_iomux_fec(void)
> +{
> + imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
> +}
> +#endif
> +
> +static void setup_iomux_uart(void)
> +{
> + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
> +}
> +
> +#ifdef CONFIG_FSL_QSPI
> +static iomux_v3_cfg_t const quadspi_pads[] = {
> + MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
> + MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
> + MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
> + MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
> + MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL),
> + MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
> +};
> +
> +int board_qspi_init(void)
> +{
> + /* Set the iomux */
> + imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads));
> +
> + /* Set the clock */
> + set_clk_qspi();
> +
> + return 0;
> +}
> +#endif
> +
> +#ifdef CONFIG_FSL_ESDHC
> +
> +#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0)
> +#define USDHC1_PWR_GPIO IMX_GPIO_NR(5, 2)
> +#define USDHC3_PWR_GPIO IMX_GPIO_NR(6, 11)
> +
> +static struct fsl_esdhc_cfg usdhc_cfg[3] = {
> + {USDHC1_BASE_ADDR, 0, 4},
> + {USDHC3_BASE_ADDR},
> +};
> +
> +static int mmc_get_env_devno(void)
> +{
> + struct bootrom_sw_info **p =
> + (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
> +
> + u8 boot_type = (*p)->boot_dev_type;
> + u8 dev_no = (*p)->boot_dev_instance;
> +
> + /* If not boot from sd/mmc, use default value */
> + if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC))
> + return CONFIG_SYS_MMC_ENV_DEV;
> +
> + if (2 == dev_no)
> + dev_no--;
> +
> + return dev_no;
> +}
> +
> +static int mmc_map_to_kernel_blk(int dev_no)
> +{
> + if (1 == dev_no)
> + dev_no++;
> +
> + return dev_no;
> +}
> +
> +int board_mmc_getcd(struct mmc *mmc)
> +{
> + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
> + int ret = 0;
> +
> + switch (cfg->esdhc_base) {
> + case USDHC1_BASE_ADDR:
> + ret = !gpio_get_value(USDHC1_CD_GPIO);
> + break;
> + case USDHC3_BASE_ADDR:
> + ret = 1; /* Assume uSDHC3 emmc is always present */
> + break;
> + }
> +
> + return ret;
> +}
> +
> +int board_mmc_init(bd_t *bis)
> +{
> + int i, ret;
> + /*
> + * According to the board_mmc_init() the following map is done:
> + * (U-boot device node) (Physical Port)
> + * mmc0 USDHC1
> + * mmc2 USDHC3 (eMMC)
> + */
> + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
> + switch (i) {
> + case 0:
> + imx_iomux_v3_setup_multiple_pads(
> + usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
> + gpio_request(USDHC1_CD_GPIO, "usdhc1_cd");
> + gpio_direction_input(USDHC1_CD_GPIO);
> + gpio_request(USDHC1_PWR_GPIO, "usdhc1_pwr");
> + gpio_direction_output(USDHC1_PWR_GPIO, 0);
> + udelay(500);
> + gpio_direction_output(USDHC1_PWR_GPIO, 1);
> + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
> + break;
> + case 1:
> + imx_iomux_v3_setup_multiple_pads(
> + usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads));
> + gpio_request(USDHC3_PWR_GPIO, "usdhc3_pwr");
> + gpio_direction_output(USDHC3_PWR_GPIO, 0);
> + udelay(500);
> + gpio_direction_output(USDHC3_PWR_GPIO, 1);
> + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
> + break;
> + default:
> + printf("Warning: you configured more USDHC controllers"
> + "(%d) than supported by the board\n", i + 1);
> + return -EINVAL;
> + }
> +
> + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +int check_mmc_autodetect(void)
static ?
> +{
> + char *autodetect_str = getenv("mmcautodetect");
> +
> + if ((autodetect_str != NULL) &&
> + (strcmp(autodetect_str, "yes") == 0)) {
> + return 1;
> + }
> +
> + return 0;
> +}
> +
> +void board_late_mmc_init(void)
board_late_<something> are global and defined __weak somewhere else.
This should be static, better without board_late_ in the name.
> +{
> + char cmd[32];
> + char mmcblk[32];
> + u32 dev_no = mmc_get_env_devno();
> +
> + if (!check_mmc_autodetect())
> + return;
> +
> + setenv_ulong("mmcdev", dev_no);
> +
> + /* Set mmcblk env */
> + sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
> + mmc_map_to_kernel_blk(dev_no));
> + setenv("mmcroot", mmcblk);
> +
> + sprintf(cmd, "mmc dev %d", dev_no);
> + run_command(cmd, 0);
> +}
> +
> +#endif
> +
> +#ifdef CONFIG_FEC_MXC
> +int board_eth_init(bd_t *bis)
> +{
> + int ret;
> +
> + setup_iomux_fec();
> +
> + ret = fecmxc_initialize_multi(bis, 0,
> + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
> + if (ret)
> + printf("FEC1 MXC: %s:failed\n", __func__);
> +
> + return ret;
> +}
> +
> +static int setup_fec(void)
> +{
> + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
> + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
> +
> + /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
> + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
> + (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
> + IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
> +
> + return set_clk_enet(ENET_125MHz);
> +}
> +
> +
> +int board_phy_config(struct phy_device *phydev)
> +{
> + /* enable rgmii rxc skew and phy mode select to RGMII copper */
> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x21);
> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x7ea8);
> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x2f);
> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x71b7);
> +
> + if (phydev->drv->config)
> + phydev->drv->config(phydev);
> + return 0;
> +}
> +#endif
> +
> +int board_early_init_f(void)
> +{
> + setup_iomux_uart();
> +
> + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
> +
> + return 0;
> +}
> +
> +int board_init(void)
> +{
> + /* address of boot parameters */
> + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
> +
> + imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads));
> +
> + iox74lv_init();
> +
> +#ifdef CONFIG_FEC_MXC
> + setup_fec();
> +#endif
> +
> +#ifdef CONFIG_SYS_USE_NAND
> + setup_gpmi_nand();
> +#endif
> +
> +#ifdef CONFIG_FSL_QSPI
> + board_qspi_init();
> +#endif
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_CMD_BMODE
> +static const struct boot_mode board_boot_modes[] = {
> + /* 4 bit bus width */
> + {"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},
> + {"emmc", MAKE_CFGVAL(0x10, 0x2a, 0x00, 0x00)},
> + /* TODO: Nand */
> + {"qspi", MAKE_CFGVAL(0x00, 0x40, 0x00, 0x00)},
> + {NULL, 0},
> +};
> +#endif
> +
> +#ifdef CONFIG_POWER
> +#define I2C_PMIC 0
> +int power_init_board(void)
For example, this is ok because it is defined weak in lib/board
> +{
> + struct pmic *p;
> + int ret;
> + unsigned int reg, rev_id;
> +
> + ret = power_pfuze3000_init(I2C_PMIC);
> + if (ret)
> + return ret;
> +
> + p = pmic_get("PFUZE3000");
> + ret = pmic_probe(p);
> + if (ret)
> + return ret;
> +
> + pmic_reg_read(p, PFUZE3000_DEVICEID, ®);
> + pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
> + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
> +
> + /* disable Low Power Mode during standby mode */
> + pmic_reg_read(p, PFUZE3000_LDOGCTL, ®);
> + reg |= 0x1;
> + pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
> +
> + return 0;
> +}
> +#endif
> +
> +int board_late_init(void)
> +{
> +#ifdef CONFIG_CMD_BMODE
> + add_board_boot_modes(board_boot_modes);
> +#endif
> +
> +#ifdef CONFIG_ENV_IS_IN_MMC
> + board_late_mmc_init();
> +#endif
> +
> + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
> +
> + set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
> +
> + return 0;
> +}
> +
> +u32 get_board_rev(void)
> +{
> + return get_cpu_rev();
> +}
> +
> +int checkboard(void)
> +{
> + puts("Board: i.MX7D SABRESD\n");
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_USB_EHCI_MX7
> +iomux_v3_cfg_t const usb_otg1_pads[] = {
> + MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +iomux_v3_cfg_t const usb_otg2_pads[] = {
> + MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +int board_ehci_hcd_init(int port)
> +{
> + switch (port) {
> + case 0:
> + imx_iomux_v3_setup_multiple_pads(usb_otg1_pads,
> + ARRAY_SIZE(usb_otg1_pads));
> + break;
> + case 1:
> + imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
> + ARRAY_SIZE(usb_otg2_pads));
> + break;
> + default:
> + printf("MXC USB port %d not yet supported\n", port);
> + return -EINVAL;
> + }
> + return 0;
> +}
> +#endif
> diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig
> new file mode 100644
> index 0000000..879847c
> --- /dev/null
> +++ b/configs/mx7dsabresd_defconfig
> @@ -0,0 +1,10 @@
> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg,MX7D"
> +CONFIG_ARM=y
> +CONFIG_TARGET_MX7DSABRESD=y
> +CONFIG_SYS_MALLOC_F=y
> +CONFIG_SYS_MALLOC_F_LEN=0x400
> +# CONFIG_CMD_BOOTD is not set
> +# CONFIG_CMD_SETEXPR is not set
> +# CONFIG_CMD_IMI is not set
> +# CONFIG_CMD_IMLS is not set
> +# CONFIG_CMD_XIMG is not set
> diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h
> new file mode 100644
> index 0000000..3747237
> --- /dev/null
> +++ b/include/configs/mx7_common.h
> @@ -0,0 +1,21 @@
> +/*
> + * Copyright (C) 2015 Freescale Semiconductor, Inc.
> + *
> + * Configuration settings for the Freescale i.MX7.
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +
> +#ifndef __MX7_COMMON_H
> +#define __MX7_COMMON_H
> +
> +#define CONFIG_MXC_GPT_HCLK
> +
> +#define CONFIG_SYSCOUNTER_TIMER
> +#define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */
> +
> +#define CONFIG_IOMUX_LPSR
> +#define CONFIG_IMX_FIXED_IVT_OFFSET
> +
> +#endif
> diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h
> new file mode 100644
> index 0000000..b84590a
> --- /dev/null
> +++ b/include/configs/mx7dsabresd.h
> @@ -0,0 +1,355 @@
> +/*
> + * Copyright (C) 2015 Freescale Semiconductor, Inc.
> + *
> + * Configuration settings for the Freescale i.MX7D SABRESD board.
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef __MX7D_SABRESD_CONFIG_H
> +#define __MX7D_SABRESD_CONFIG_H
> +
> +#include <asm/arch/imx-regs.h>
> +#include <linux/sizes.h>
> +#include "mx7_common.h"
> +#include <asm/imx-common/gpio.h>
> +
> +#define CONFIG_MX7
> +#define CONFIG_ROM_UNIFIED_SECTIONS
> +#define CONFIG_SYS_GENERIC_BOARD
> +#define CONFIG_DISPLAY_CPUINFO
> +#define CONFIG_DISPLAY_BOARDINFO
> +
> +#define CONFIG_DBG_MONITOR
> +/* uncomment for PLUGIN mode support */
> +/* #define CONFIG_USE_PLUGIN */
> +
> +/* uncomment for SECURE mode support */
> +/* #define CONFIG_SECURE_BOOT */
> +
> +#ifdef CONFIG_SECURE_BOOT
> +#ifndef CONFIG_CSF_SIZE
> +#define CONFIG_CSF_SIZE 0x4000
> +#endif
> +#endif
You have already prepared a mx7_common.h (very good !), and I am asking
if most defines here should be not moved in the common. For example, I
agree that CONFIG_SECURE_BOOT is board specific. But then is
CONFIG_CSF_SIZE board specific ? If yes, ok, sorry. Else it is better to
have CONFIG_SECURE_BOOT and the #ifdef in the common file.
> +
> +#define CONFIG_CMDLINE_TAG
> +#define CONFIG_SETUP_MEMORY_TAGS
> +#define CONFIG_INITRD_TAG
> +#define CONFIG_REVISION_TAG
Do we support not-DT kernel ? If not, why do we need them ?
> +
> +/* Size of malloc() pool */
> +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
> +
> +#define CONFIG_BOARD_EARLY_INIT_F
> +#define CONFIG_BOARD_LATE_INIT
> +#define CONFIG_MXC_GPIO
> +
> +#define CONFIG_MXC_UART
Maybe also in common ?
> +#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
> +
> +/* allow to overwrite serial and ethaddr */
> +#define CONFIG_ENV_OVERWRITE
> +#define CONFIG_CONS_INDEX 1
> +#define CONFIG_BAUDRATE 115200
> +
> +#define CONFIG_CMD_FUSE
> +#ifdef CONFIG_CMD_FUSE
> +#define CONFIG_MXC_OCOTP
> +#endif
as well as these ones, maybe.
I think you can take as reference mx6_common.h to get a quick view which
defines can be set as global.
> +
> +/* MMC Configs */
> +#define CONFIG_FSL_ESDHC
> +#define CONFIG_FSL_USDHC
> +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
> +
> +#define CONFIG_MMC
> +#define CONFIG_CMD_MMC
> +#define CONFIG_GENERIC_MMC
> +#define CONFIG_CMD_FAT
> +#define CONFIG_DOS_PARTITION
> +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
> +
> +#define PHYS_SDRAM_SIZE SZ_1G
> +
> +#define CONFIG_CMD_PING
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_MII
> +#define CONFIG_FEC_MXC
> +#define CONFIG_MII
> +#define CONFIG_FEC_XCV_TYPE RGMII
> +#define CONFIG_ETHPRIME "FEC"
> +#define CONFIG_FEC_MXC_PHYADDR 0
> +
> +#define CONFIG_PHYLIB
> +#define CONFIG_PHY_BROADCOM
> +#define CONFIG_FEC_DMA_MINALIGN 64
> +
> +/* ENET1 */
> +#define IMX_FEC_BASE ENET_IPS_BASE_ADDR
> +
> +/* PMIC */
> +#define CONFIG_POWER
> +#define CONFIG_POWER_I2C
> +#define CONFIG_POWER_PFUZE3000
> +#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
> +
> +#undef CONFIG_BOOTM_NETBSD
> +#undef CONFIG_BOOTM_PLAN9
> +#undef CONFIG_BOOTM_RTEMS
> +
> +#undef CONFIG_CMD_EXPORTENV
> +#undef CONFIG_CMD_IMPORTENV
> +
> +/* I2C configs */
> +#define CONFIG_CMD_I2C
> +#define CONFIG_SYS_I2C
> +#define CONFIG_SYS_I2C_MXC
> +#define CONFIG_SYS_I2C_MXC_I2C1
> +#define CONFIG_SYS_I2C_SPEED 100000
> +
> +#undef CONFIG_CMD_IMLS
> +
> +#define CONFIG_BOOTDELAY 3
> +
> +#define CONFIG_LOADADDR 0x80800000
> +#define CONFIG_SYS_TEXT_BASE 0x87800000
> +
> +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
> +#ifdef CONFIG_SYS_BOOT_NAND
> +#define CONFIG_MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),-(rootfs) "
> +#else
> +#define CONFIG_MFG_NAND_PARTITION ""
> +#endif
> +
> +#define CONFIG_MFG_ENV_SETTINGS \
> + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
> + "rdinit=/linuxrc " \
> + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \
> + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
> + "g_mass_storage.iSerialNumber=\"\" "\
> + CONFIG_MFG_NAND_PARTITION \
> + "clk_ignore_unused "\
> + "\0" \
> + "initrd_addr=0x83800000\0" \
> + "initrd_high=0xffffffff\0" \
> + "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
> +
> +#if defined(CONFIG_SYS_BOOT_NAND)
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + CONFIG_MFG_ENV_SETTINGS \
> + "fdt_addr=0x83000000\0" \
> + "fdt_high=0xffffffff\0" \
> + "console=ttymxc0\0" \
> + "bootargs=console=ttymxc0,115200 ubi.mtd=3 " \
> + "root=ubi0:rootfs rootfstype=ubifs " \
> + "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),-(rootfs)\0"\
> + "bootcmd=nand read ${loadaddr} 0x4000000 0x800000;"\
> + "nand read ${fdt_addr} 0x5000000 0x100000;"\
> + "bootz ${loadaddr} - ${fdt_addr}\0"
> +
> +#else
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + CONFIG_MFG_ENV_SETTINGS \
> + "script=boot.scr\0" \
> + "image=zImage\0" \
> + "console=ttymxc0\0" \
> + "fdt_high=0xffffffff\0" \
> + "initrd_high=0xffffffff\0" \
> + "fdt_file=imx7d-sdb.dtb\0" \
> + "fdt_addr=0x83000000\0" \
> + "boot_fdt=try\0" \
> + "ip_dyn=yes\0" \
> + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
> + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
> + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
> + "mmcautodetect=yes\0" \
> + "mmcargs=setenv bootargs console=${console},${baudrate} " \
> + "root=${mmcroot}\0" \
> + "loadbootscript=" \
> + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
> + "bootscript=echo Running bootscript from mmc ...; " \
> + "source\0" \
> + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
> + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
> + "mmcboot=echo Booting from mmc ...; " \
> + "run mmcargs; " \
> + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
> + "if run loadfdt; then " \
> + "bootz ${loadaddr} - ${fdt_addr}; " \
> + "else " \
> + "if test ${boot_fdt} = try; then " \
> + "bootz; " \
> + "else " \
> + "echo WARN: Cannot load the DT; " \
> + "fi; " \
> + "fi; " \
> + "else " \
> + "bootz; " \
> + "fi;\0" \
> + "netargs=setenv bootargs console=${console},${baudrate} " \
> + "root=/dev/nfs " \
> + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
> + "netboot=echo Booting from net ...; " \
> + "run netargs; " \
> + "if test ${ip_dyn} = yes; then " \
> + "setenv get_cmd dhcp; " \
> + "else " \
> + "setenv get_cmd tftp; " \
> + "fi; " \
> + "${get_cmd} ${image}; " \
> + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
> + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
> + "bootz ${loadaddr} - ${fdt_addr}; " \
> + "else " \
> + "if test ${boot_fdt} = try; then " \
> + "bootz; " \
> + "else " \
> + "echo WARN: Cannot load the DT; " \
> + "fi; " \
> + "fi; " \
> + "else " \
> + "bootz; " \
> + "fi;\0"
> +
> +#define CONFIG_BOOTCOMMAND \
> + "mmc dev ${mmcdev};" \
> + "mmc dev ${mmcdev}; if mmc rescan; then " \
> + "if run loadbootscript; then " \
> + "run bootscript; " \
> + "else " \
> + "if run loadimage; then " \
> + "run mmcboot; " \
> + "else run netboot; " \
> + "fi; " \
> + "fi; " \
> + "else run netboot; fi"
> +#endif
> +
Nothing against this - you are the board maintainer and you decide which
is the default environment. However, as this is a new board, what about
to switch to the distro bootcmd ?
> +/* Miscellaneous configurable options */
> +#define CONFIG_SYS_LONGHELP
> +#define CONFIG_SYS_HUSH_PARSER
> +#define CONFIG_AUTO_COMPLETE
> +#define CONFIG_SYS_CBSIZE 1024
> +#define CONFIG_SYS_MAXARGS 256
> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> +
> +#define CONFIG_CMD_MEMTEST
> +#define CONFIG_SYS_MEMTEST_START 0x80000000
> +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000)
> +
> +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
> +#define CONFIG_SYS_HZ 1000
> +
> +#define CONFIG_CMDLINE_EDITING
> +#define CONFIG_STACKSIZE SZ_128K
> +
> +/* Physical Memory Map */
> +#define CONFIG_NR_DRAM_BANKS 1
> +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
> +
> +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
> +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
> +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
> +
> +#define CONFIG_SYS_INIT_SP_OFFSET \
> + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> +#define CONFIG_SYS_INIT_SP_ADDR \
> + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> +
> +/* FLASH and environment organization */
> +#define CONFIG_SYS_NO_FLASH
> +
> +#define CONFIG_ENV_SIZE SZ_8K
> +
> +#ifdef CONFIG_SYS_BOOT_QSPI
> +#define CONFIG_SYS_USE_QSPI
> +#define CONFIG_ENV_IS_IN_SPI_FLASH
> +#elif defined CONFIG_SYS_BOOT_NAND
> +#define CONFIG_SYS_USE_NAND
> +#define CONFIG_ENV_IS_IN_NAND
> +#else
> +#define CONFIG_ENV_IS_IN_MMC
> +#endif
> +
> +#ifdef CONFIG_SYS_USE_NAND
> +#define CONFIG_CMD_NAND
> +#define CONFIG_CMD_NAND_TRIMFFS
> +
> +/* NAND stuff */
> +#define CONFIG_NAND_MXS
> +#define CONFIG_SYS_MAX_NAND_DEVICE 1
> +#define CONFIG_SYS_NAND_BASE 0x40000000
> +#define CONFIG_SYS_NAND_5_ADDR_CYCLE
> +#define CONFIG_SYS_NAND_ONFI_DETECTION
> +
> +/* DMA stuff, needed for GPMI/MXS NAND support */
> +#define CONFIG_APBH_DMA
> +#define CONFIG_APBH_DMA_BURST
> +#define CONFIG_APBH_DMA_BURST8
> +#endif
> +
> +#ifdef CONFIG_SYS_USE_QSPI
> +#define CONFIG_FSL_QSPI /* enable the QUADSPI driver */
> +#define CONFIG_QSPI_BASE QSPI1_IPS_BASE_ADDR
> +#define CONFIG_QSPI_MEMMAP_BASE QSPI0_ARB_BASE_ADDR
> +
> +#define CONFIG_CMD_SF
> +#define CONFIG_SPI_FLASH
> +#define CONFIG_SPI_FLASH_MACRONIX
> +#define CONFIG_SPI_FLASH_BAR
> +#define CONFIG_SF_DEFAULT_BUS 0
> +#define CONFIG_SF_DEFAULT_CS 0
> +#define CONFIG_SF_DEFAULT_SPEED 40000000
> +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
> +#endif
> +
> +#if defined(CONFIG_ENV_IS_IN_MMC)
> +#define CONFIG_ENV_OFFSET (8 * SZ_64K)
> +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
> +#define CONFIG_ENV_OFFSET (768 * 1024)
> +#define CONFIG_ENV_SECT_SIZE (64 * 1024)
> +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
> +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
> +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
> +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
> +#elif defined(CONFIG_ENV_IS_IN_NAND)
> +#undef CONFIG_ENV_SIZE
> +#define CONFIG_ENV_OFFSET (8 << 20)
> +#define CONFIG_ENV_SECT_SIZE (128 << 10)
> +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
> +#endif
> +
> +#ifdef CONFIG_SYS_USE_NAND
> +#define CONFIG_SYS_FSL_USDHC_NUM 1
> +#else
> +#define CONFIG_SYS_FSL_USDHC_NUM 2
> +#endif
> +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
> +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
> +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
> +
> +#define CONFIG_OF_LIBFDT
> +#define CONFIG_CMD_BOOTZ
> +
> +#define CONFIG_CMD_BMODE
> +
> +#ifndef CONFIG_SYS_DCACHE_OFF
> +#define CONFIG_CMD_CACHE
> +#endif
> +
> +/* USB Configs */
> +#define CONFIG_CMD_USB
> +#define CONFIG_USB_EHCI
> +#define CONFIG_USB_EHCI_MX7
> +#define CONFIG_USB_STORAGE
> +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
> +#define CONFIG_USB_HOST_ETHER
> +#define CONFIG_USB_ETHER_ASIX
> +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
> +#define CONFIG_MXC_USB_FLAGS 0
> +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
> +
> +#define CONFIG_IMX_THERMAL
> +
> +#endif /* __CONFIG_H */
>
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
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