[U-Boot] [PATCH V2] ARM: imx: fsl_esdhc: fix usage of low 4 bits of sysctl register

[Stefano Babic]

On 04/12/2015 20:32, Eric Nelson wrote:
> The low four bits of the SYSCTL register are reserved on the USDHC
> controller on i.MX6 and i.MX7 processors, but are used for clocking
> operations on earlier models.
> 
> Guard against their usage by hiding the bit mask macros on those
> processors.
> 
> These bits are used to prevent glitches when changing clocks on
> i.MX35 et al. Use the RSTA bit instead for i.MX6 and i.MX7.
> 
> From the i.MX6DQ RM:
> 	To prevent possible glitch on the card clock, clear the
> 	FRC_SDCLK_ON bit when changing clock divisor value(SDCLKFS
> 	or DVS in System Control Register) or setting RSTA bit.
> 
> Signed-off-by: Eric Nelson <eric at nelint.com>
> ---
> V2 uses CONFIG_FSL_USDHC instead of CONFIG_MX6 in fsl_esdhc.h
>  drivers/mmc/fsl_esdhc.c | 15 +++++++++++++--
>  include/fsl_esdhc.h     |  2 ++
>  2 files changed, 15 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
> index c5054d6..1ccc576 100644
> --- a/drivers/mmc/fsl_esdhc.c
> +++ b/drivers/mmc/fsl_esdhc.c
> @@ -502,15 +502,22 @@ static void set_sysctl(struct mmc *mmc, uint clock)
>  
>  	clk = (pre_div << 8) | (div << 4);
>  
> +#ifdef CONFIG_FSL_USDHC
> +	esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
> +#else
>  	esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
> +#endif
>  
>  	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
>  
>  	udelay(10000);
>  
> -	clk = SYSCTL_PEREN | SYSCTL_CKEN;
> +#ifdef CONFIG_FSL_USDHC
> +	esdhc_clrbits32(&regs->sysctl, SYSCTL_RSTA);
> +#else
> +	esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
> +#endif
>  
> -	esdhc_setbits32(&regs->sysctl, clk);
>  }
>  
>  #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
> @@ -585,7 +592,9 @@ static int esdhc_init(struct mmc *mmc)
>  	esdhc_write32(&regs->scr, 0x00000040);
>  #endif
>  
> +#ifndef CONFIG_FSL_USDHC
>  	esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
> +#endif
>  
>  	/* Set the initial clock speed */
>  	mmc_set_clock(mmc, 400000);
> @@ -657,8 +666,10 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
>  	/* First reset the eSDHC controller */
>  	esdhc_reset(regs);
>  
> +#ifndef CONFIG_FSL_USDHC
>  	esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
>  				| SYSCTL_IPGEN | SYSCTL_CKEN);
> +#endif
>  
>  	writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten);
>  	memset(&cfg->cfg, 0, sizeof(cfg->cfg));
> diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
> index aa1b4cf..a4b87ce 100644
> --- a/include/fsl_esdhc.h
> +++ b/include/fsl_esdhc.h
> @@ -25,10 +25,12 @@
>  #define SYSCTL_INITA		0x08000000
>  #define SYSCTL_TIMEOUT_MASK	0x000f0000
>  #define SYSCTL_CLOCK_MASK	0x0000fff0
> +#if !defined(CONFIG_FSL_USDHC)
>  #define SYSCTL_CKEN		0x00000008
>  #define SYSCTL_PEREN		0x00000004
>  #define SYSCTL_HCKEN		0x00000002
>  #define SYSCTL_IPGEN		0x00000001
> +#endif
>  #define SYSCTL_RSTA		0x01000000
>  #define SYSCTL_RSTC		0x02000000
>  #define SYSCTL_RSTD		0x04000000
> 

Reviewed-by: Stefano Babic <sbabic at denx.de>

Best regards,
Stefano Babic

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