[U-Boot] [PATCH v4 1/2] Errata/ARM57: Add basic constructs to handle and apply A57 specific erratas

[Albert ARIBAUD]

Hello Bhupesh,

On Fri, 23 Jan 2015 15:50:04 +0530, Bhupesh Sharma <bhupesh.sharma at freescale.com> wrote:
> This patch adds basic constructs in the ARMv8 u-boot code
> to handle and apply Cortex-A57 specific erratas.
> 
> As and example, the framework showcases how erratas 833069, 826974
> and 828024 can be handled and applied.
> 
> Later on this framework can be extended to include other
> erratas.
> 
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com>
> ---
> Changes from v3:
> 	- Addressed comments from Scott regarding backward branching &
> 	  correct masking from A53's MIDR_EL1.
> 
> Changes from v2:
> 	- Addressed comments regarding incorrect handling of bl and ret
> 	  sequences.
> 	- Reorganized the code to be more readable.
> 
> Changes from v1:
> 	- Addressed Yorks' comments about x29 corruption.
> 
>  arch/arm/cpu/armv8/start.S   |   45 ++++++++++++++++++++++++++++++++++++++++++
>  arch/arm/include/asm/macro.h |   22 +++++++++++++++++++++
>  2 files changed, 67 insertions(+)
> 
> diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
> index 4b11aa4..540a5db 100644
> --- a/arch/arm/cpu/armv8/start.S
> +++ b/arch/arm/cpu/armv8/start.S
> @@ -67,6 +67,9 @@ reset:
>  	msr	cpacr_el1, x0			/* Enable FP/SIMD */
>  0:
>  
> +	/* Apply ARM core specific erratas */
> +	bl	apply_core_errata
> +
>  	/*
>  	 * Cache/BPB/TLB Invalidate
>  	 * i-cache is invalidated before enabled in icache_enable()
> @@ -97,6 +100,48 @@ master_cpu:
>  
>  /*-----------------------------------------------------------------------*/
>  
> +WEAK(apply_core_errata)
> +
> +	mov	x29, lr			/* Save LR */
> +	/* For now, we support Cortex-A57 specific errata only */
> +
> +	/* Check if we are running on a Cortex-A57 core */
> +	branch_if_a57_core x0, apply_a57_core_errata
> +0:
> +	mov	lr, x29			/* Restore LR */
> +	ret
> +
> +apply_a57_core_errata:
> +
> +#ifdef CONFIG_ARM_ERRATA_828024
> +	mrs	x0, S3_1_c15_c2_0	/* cpuactlr_el1 */
> +	/* Disable non-allocate hint of w-b-n-a memory type */
> +	mov	x0, #0x1 << 49
> +	/* Disable write streaming no L1-allocate threshold */
> +	mov	x0, #0x3 << 25
> +	/* Disable write streaming no-allocate threshold */
> +	mov	x0, #0x3 << 27
> +	msr	S3_1_c15_c2_0, x0	/* cpuactlr_el1 */
> +#endif
> +
> +#ifdef CONFIG_ARM_ERRATA_826974
> +	mrs	x0, S3_1_c15_c2_0	/* cpuactlr_el1 */
> +	/* Disable speculative load execution ahead of a DMB */
> +	mov	x0, #0x1 << 59
> +	msr	S3_1_c15_c2_0, x0	/* cpuactlr_el1 */
> +#endif
> +
> +#ifdef CONFIG_ARM_ERRATA_833069
> +	mrs	x0, S3_1_c15_c2_0	/* cpuactlr_el1 */
> +	/* Disable Enable Invalidates of BTB bit */
> +	and	x0, x0, #0xE
> +	msr	S3_1_c15_c2_0, x0	/* cpuactlr_el1 */
> +#endif
> +	b 0b
> +ENDPROC(apply_core_errata)
> +
> +/*-----------------------------------------------------------------------*/
> +
>  WEAK(lowlevel_init)
>  	mov	x29, lr			/* Save LR */
>  
> diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h
> index 1c8c425..5f7c7e0 100644
> --- a/arch/arm/include/asm/macro.h
> +++ b/arch/arm/include/asm/macro.h
> @@ -74,6 +74,28 @@ lr	.req	x30
>  .endm
>  
>  /*
> + * Branch if current processor is a Cortex-A57 core.
> + */
> +.macro	branch_if_a57_core, xreg, a57_label
> +	mrs	\xreg, midr_el1
> +	lsr	\xreg, \xreg, #4
> +	and	\xreg, \xreg, #0x00000FFF
> +	cmp	\xreg, #0xD07		/* Cortex-A57 MPCore processor. */
> +	b.eq	\a57_label
> +.endm
> +
> +/*
> + * Branch if current processor is a Cortex-A53 core.
> + */
> +.macro	branch_if_a53_core, xreg, a53_label
> +	mrs	\xreg, midr_el1
> +	lsr	\xreg, \xreg, #4
> +	and	\xreg, \xreg, #0x00000FFF
> +	cmp	\xreg, #0xD03		/* Cortex-A53 MPCore processor. */
> +	b.eq	\a53_label
> +.endm
> +
> +/*
>   * Branch if current processor is a slave,
>   * choose processor with all zero affinity value as the master.
>   */
> -- 
> 1.7.9.5
> 
> 

Applied to u-boot-arm/master, thanks!

Amicalement,
-- 
Albert.