[U-Boot] [PATCH] ARMv8: Bug fix of dcache_disable()

[Mark Rutland]

On Mon, Feb 09, 2015 at 08:51:59AM +0000, fenghua at phytium.com.cn wrote:
> From: David Feng <fenghua at phytium.com.cn>
> 
> The cache disable operation shoud be performed after flush_dcache_all().
> If cache disable operation is performed before
> flush_dcache_all(), flush_dcache_all() store data directly to memory
> and may be overrided by data copy in cache.

The reasoning above (and hence this patch) is wrong.

While the caches are on, they can allocate lines for any portion of the
address space with cacheable attributes, and can acquire dirty cache
lines from other CPUs. Additionally, there is no restriction preventing
lines from migrating between levels of cache while they are active.

So calling flush_dcache_all (which performs maintenance by Set/Way)
while the caches are enabled is wrong. Per the architecture it provides
no guarantee whatsoever.

To empty the caches by Set/Way, they must first be disabled. Note that
this only guarantees that the caches are empty; not where the data went.
Other CPUs might acquire dirty lines, or the data might only reach a
system cache rather than memory.

If you need certain portions of data to be flushed out to memory, then
those must be flushed by VA. If flush_dcache_all performs any memory
accesses before it has completed Set/Way maintenance, it is buggy.

Thanks,
Mark.

> 
> Signed-off-by: David Feng <fenghua at phytium.com.cn>
> ---
>  arch/arm/cpu/armv8/cache_v8.c |    3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
> index 9dbcdf2..dc2fc8c 100644
> --- a/arch/arm/cpu/armv8/cache_v8.c
> +++ b/arch/arm/cpu/armv8/cache_v8.c
> @@ -124,9 +124,10 @@ void dcache_disable(void)
>  	if (!(sctlr & CR_C))
>  		return;
>  
> +	flush_dcache_all();
> +
>  	set_sctlr(sctlr & ~(CR_C|CR_M));
>  
> -	flush_dcache_all();
>  	__asm_invalidate_tlb_all();
>  }
>  
> -- 
> 1.7.9.5
> 
> 
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