[U-Boot] [PATCH v2 05/10] ARM: remove devkit3250 board support

Masahiro Yamada yamada.m at jp.panasonic.com
Tue Feb 10 08:00:26 CET 2015


This is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m at jp.panasonic.com>
Cc: Vladimir Zapolskiy <vz at mleia.com>
---

Changes in v2: None

 arch/arm/Kconfig                              |   5 -
 arch/arm/cpu/arm926ejs/Makefile               |   1 -
 arch/arm/cpu/arm926ejs/lpc32xx/Makefile       |   8 --
 arch/arm/cpu/arm926ejs/lpc32xx/clk.c          | 104 -----------------
 arch/arm/cpu/arm926ejs/lpc32xx/cpu.c          |  57 ----------
 arch/arm/cpu/arm926ejs/lpc32xx/devices.c      |  39 -------
 arch/arm/cpu/arm926ejs/lpc32xx/timer.c        |  82 --------------
 arch/arm/include/asm/arch-lpc32xx/clk.h       | 157 --------------------------
 arch/arm/include/asm/arch-lpc32xx/config.h    |  59 ----------
 arch/arm/include/asm/arch-lpc32xx/cpu.h       |  51 ---------
 arch/arm/include/asm/arch-lpc32xx/emc.h       |  79 -------------
 arch/arm/include/asm/arch-lpc32xx/sys_proto.h |  12 --
 arch/arm/include/asm/arch-lpc32xx/timer.h     |  61 ----------
 arch/arm/include/asm/arch-lpc32xx/uart.h      | 101 -----------------
 arch/arm/include/asm/arch-lpc32xx/wdt.h       |  38 -------
 board/timll/devkit3250/Kconfig                |  15 ---
 board/timll/devkit3250/MAINTAINERS            |   6 -
 board/timll/devkit3250/Makefile               |   8 --
 board/timll/devkit3250/devkit3250.c           |  52 ---------
 configs/devkit3250_defconfig                  |   2 -
 doc/README.scrapyard                          |   1 +
 drivers/serial/Makefile                       |   1 -
 drivers/serial/lpc32xx_hsuart.c               |  89 ---------------
 drivers/serial/serial.c                       |   2 -
 include/configs/devkit3250.h                  | 101 -----------------
 include/serial.h                              |   1 -
 26 files changed, 1 insertion(+), 1131 deletions(-)
 delete mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/Makefile
 delete mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/clk.c
 delete mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
 delete mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/devices.c
 delete mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/timer.c
 delete mode 100644 arch/arm/include/asm/arch-lpc32xx/clk.h
 delete mode 100644 arch/arm/include/asm/arch-lpc32xx/config.h
 delete mode 100644 arch/arm/include/asm/arch-lpc32xx/cpu.h
 delete mode 100644 arch/arm/include/asm/arch-lpc32xx/emc.h
 delete mode 100644 arch/arm/include/asm/arch-lpc32xx/sys_proto.h
 delete mode 100644 arch/arm/include/asm/arch-lpc32xx/timer.h
 delete mode 100644 arch/arm/include/asm/arch-lpc32xx/uart.h
 delete mode 100644 arch/arm/include/asm/arch-lpc32xx/wdt.h
 delete mode 100644 board/timll/devkit3250/Kconfig
 delete mode 100644 board/timll/devkit3250/MAINTAINERS
 delete mode 100644 board/timll/devkit3250/Makefile
 delete mode 100644 board/timll/devkit3250/devkit3250.c
 delete mode 100644 configs/devkit3250_defconfig
 delete mode 100644 drivers/serial/lpc32xx_hsuart.c
 delete mode 100644 include/configs/devkit3250.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index cbed2f4..b0b7eaf 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -241,10 +241,6 @@ config TARGET_MAXBCM
 	bool "Support maxbcm"
 	select CPU_V7
 
-config TARGET_DEVKIT3250
-	bool "Support devkit3250"
-	select CPU_ARM926EJS
-
 config TARGET_MX25PDK
 	bool "Support mx25pdk"
 	select CPU_ARM926EJS
@@ -968,7 +964,6 @@ source "board/ti/am43xx/Kconfig"
 source "board/ti/ti814x/Kconfig"
 source "board/ti/ti816x/Kconfig"
 source "board/ti/tnetv107xevm/Kconfig"
-source "board/timll/devkit3250/Kconfig"
 source "board/toradex/colibri_pxa270/Kconfig"
 source "board/tqc/tqma6/Kconfig"
 source "board/trizepsiv/Kconfig"
diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile
index 607d29f..bfa365e 100644
--- a/arch/arm/cpu/arm926ejs/Makefile
+++ b/arch/arm/cpu/arm926ejs/Makefile
@@ -18,7 +18,6 @@ obj-$(CONFIG_ARMADA100) += armada100/
 obj-$(CONFIG_AT91FAMILY) += at91/
 obj-$(CONFIG_ARCH_DAVINCI) += davinci/
 obj-$(CONFIG_KIRKWOOD) += kirkwood/
-obj-$(if $(filter lpc32xx,$(SOC)),y) += lpc32xx/
 obj-$(CONFIG_MX25) += mx25/
 obj-$(CONFIG_MX27) += mx27/
 obj-$(if $(filter mxs,$(SOC)),y) += mxs/
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/Makefile b/arch/arm/cpu/arm926ejs/lpc32xx/Makefile
deleted file mode 100644
index 314f004..0000000
--- a/arch/arm/cpu/arm926ejs/lpc32xx/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y   = cpu.o clk.o devices.o timer.o
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/clk.c b/arch/arm/cpu/arm926ejs/lpc32xx/clk.c
deleted file mode 100644
index b7a44d5..0000000
--- a/arch/arm/cpu/arm926ejs/lpc32xx/clk.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * Copyright (C) 2011 by Vladimir Zapolskiy <vz at mleia.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <div64.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clk.h>
-#include <asm/io.h>
-
-static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
-
-unsigned int get_sys_clk_rate(void)
-{
-	if (readl(&clk->sysclk_ctrl) & CLK_SYSCLK_PLL397)
-		return RTC_CLK_FREQUENCY * 397;
-	else
-		return OSC_CLK_FREQUENCY;
-}
-
-unsigned int get_hclk_pll_rate(void)
-{
-	unsigned long long fin, fref, fcco, fout;
-	u32 val, m_div, n_div, p_div;
-
-	/*
-	 * Valid frequency ranges:
-	 *     1 * 10^6 <=  Fin <=  20 * 10^6
-	 *     1 * 10^6 <= Fref <=  27 * 10^6
-	 *   156 * 10^6 <= Fcco <= 320 * 10^6
-	 */
-
-	fref = fin = get_sys_clk_rate();
-	if (fin > 20000000ULL || fin < 1000000ULL)
-		return 0;
-
-	val = readl(&clk->hclkpll_ctrl);
-	m_div = ((val & CLK_HCLK_PLL_FEEDBACK_DIV_MASK) >> 1) + 1;
-	n_div = ((val & CLK_HCLK_PLL_PREDIV_MASK) >> 9) + 1;
-	if (val & CLK_HCLK_PLL_DIRECT)
-		p_div = 0;
-	else
-		p_div = ((val & CLK_HCLK_PLL_POSTDIV_MASK) >> 11) + 1;
-	p_div = 1 << p_div;
-
-	if (val & CLK_HCLK_PLL_BYPASS) {
-		do_div(fin, p_div);
-		return fin;
-	}
-
-	do_div(fref, n_div);
-	if (fref > 27000000ULL || fref < 1000000ULL)
-		return 0;
-
-	fout = fref * m_div;
-	if (val & CLK_HCLK_PLL_FEEDBACK) {
-		fcco = fout;
-		do_div(fout, p_div);
-	} else
-		fcco = fout * p_div;
-
-	if (fcco > 320000000ULL || fcco < 156000000ULL)
-		return 0;
-
-	return fout;
-}
-
-unsigned int get_hclk_clk_div(void)
-{
-	u32 val;
-
-	val = readl(&clk->hclkdiv_ctrl) & CLK_HCLK_ARM_PLL_DIV_MASK;
-
-	return 1 << val;
-}
-
-unsigned int get_hclk_clk_rate(void)
-{
-	return get_hclk_pll_rate() / get_hclk_clk_div();
-}
-
-unsigned int get_periph_clk_div(void)
-{
-	u32 val;
-
-	val = readl(&clk->hclkdiv_ctrl) & CLK_HCLK_PERIPH_DIV_MASK;
-
-	return (val >> 2) + 1;
-}
-
-unsigned int get_periph_clk_rate(void)
-{
-	if (!(readl(&clk->pwr_ctrl) & CLK_PWR_NORMAL_RUN))
-		return get_sys_clk_rate();
-
-	return get_hclk_pll_rate() / get_periph_clk_div();
-}
-
-int get_serial_clock(void)
-{
-	return get_periph_clk_rate();
-}
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
deleted file mode 100644
index 35095a9..0000000
--- a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * Copyright (C) 2011 by Vladimir Zapolskiy <vz at mleia.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/wdt.h>
-#include <asm/io.h>
-
-static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
-static struct wdt_regs  *wdt = (struct wdt_regs *)WDT_BASE;
-
-void reset_cpu(ulong addr)
-{
-	/* Enable watchdog clock */
-	setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
-
-	/* Reset pulse length is 13005 peripheral clock frames */
-	writel(13000, &wdt->pulse);
-
-	/* Force WDOG_RESET2 and RESOUT_N signal active */
-	writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1 | WDTIM_MCTRL_M_RES2,
-	       &wdt->mctrl);
-
-	while (1)
-		/* NOP */;
-}
-
-#if defined(CONFIG_ARCH_CPU_INIT)
-int arch_cpu_init(void)
-{
-	/*
-	 * It might be necessary to flush data cache, if U-boot is loaded
-	 * from kickstart bootloader, e.g. from S1L loader
-	 */
-	flush_dcache_all();
-
-	return 0;
-}
-#else
-#error "You have to select CONFIG_ARCH_CPU_INIT"
-#endif
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
-	printf("CPU:   NXP LPC32XX\n");
-	printf("CPU clock:        %uMHz\n", get_hclk_pll_rate() / 1000000);
-	printf("AHB bus clock:    %uMHz\n", get_hclk_clk_rate() / 1000000);
-	printf("Peripheral clock: %uMHz\n", get_periph_clk_rate() / 1000000);
-
-	return 0;
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
deleted file mode 100644
index b567657..0000000
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright (C) 2011 by Vladimir Zapolskiy <vz at mleia.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/uart.h>
-#include <asm/io.h>
-
-static struct clk_pm_regs    *clk  = (struct clk_pm_regs *)CLK_PM_BASE;
-static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE;
-
-void lpc32xx_uart_init(unsigned int uart_id)
-{
-	if (uart_id < 1 || uart_id > 7)
-		return;
-
-	/* Disable loopback mode, if it is set by S1L bootloader */
-	clrbits_le32(&ctrl->loop,
-		     UART_LOOPBACK(CONFIG_SYS_LPC32XX_UART));
-
-	if (uart_id < 3 || uart_id > 6)
-		return;
-
-	/* Enable UART system clock */
-	setbits_le32(&clk->uartclk_ctrl, CLK_UART(uart_id));
-
-	/* Set UART into autoclock mode */
-	clrsetbits_le32(&ctrl->clkmode,
-			UART_CLKMODE_MASK(uart_id),
-			UART_CLKMODE_AUTO(uart_id));
-
-	/* Bypass pre-divider of UART clock */
-	writel(CLK_UART_X_DIV(1) | CLK_UART_Y_DIV(1),
-	       &clk->u3clk + (uart_id - 3));
-}
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/timer.c b/arch/arm/cpu/arm926ejs/lpc32xx/timer.c
deleted file mode 100644
index dc1217e..0000000
--- a/arch/arm/cpu/arm926ejs/lpc32xx/timer.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * Copyright (C) 2011 Vladimir Zapolskiy <vz at mleia.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/timer.h>
-#include <asm/io.h>
-
-static struct timer_regs  *timer0 = (struct timer_regs *)TIMER0_BASE;
-static struct timer_regs  *timer1 = (struct timer_regs *)TIMER1_BASE;
-static struct clk_pm_regs *clk    = (struct clk_pm_regs *)CLK_PM_BASE;
-
-static void lpc32xx_timer_clock(u32 bit, int enable)
-{
-	if (enable)
-		setbits_le32(&clk->timclk_ctrl1, bit);
-	else
-		clrbits_le32(&clk->timclk_ctrl1, bit);
-}
-
-static void lpc32xx_timer_reset(struct timer_regs *timer, u32 freq)
-{
-	writel(TIMER_TCR_COUNTER_RESET,   &timer->tcr);
-	writel(TIMER_TCR_COUNTER_DISABLE, &timer->tcr);
-	writel(0, &timer->tc);
-	writel(0, &timer->pr);
-
-	/* Count mode is every rising PCLK edge */
-	writel(TIMER_CTCR_MODE_TIMER, &timer->ctcr);
-
-	/* Set prescale counter value */
-	writel((get_periph_clk_rate() / freq) - 1, &timer->pr);
-}
-
-static void lpc32xx_timer_count(struct timer_regs *timer, int enable)
-{
-	if (enable)
-		writel(TIMER_TCR_COUNTER_ENABLE,  &timer->tcr);
-	else
-		writel(TIMER_TCR_COUNTER_DISABLE, &timer->tcr);
-}
-
-int timer_init(void)
-{
-	lpc32xx_timer_clock(CLK_TIMCLK_TIMER0, 1);
-	lpc32xx_timer_reset(timer0, CONFIG_SYS_HZ);
-	lpc32xx_timer_count(timer0, 1);
-
-	return 0;
-}
-
-ulong get_timer(ulong base)
-{
-	return readl(&timer0->tc) - base;
-}
-
-void __udelay(unsigned long usec)
-{
-	lpc32xx_timer_clock(CLK_TIMCLK_TIMER1, 1);
-	lpc32xx_timer_reset(timer1, CONFIG_SYS_HZ * 1000);
-	lpc32xx_timer_count(timer1, 1);
-
-	while (readl(&timer1->tc) < usec)
-		/* NOP */;
-
-	lpc32xx_timer_count(timer1, 0);
-	lpc32xx_timer_clock(CLK_TIMCLK_TIMER1, 0);
-}
-
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-ulong get_tbclk(void)
-{
-	return CONFIG_SYS_HZ;
-}
diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h b/arch/arm/include/asm/arch-lpc32xx/clk.h
deleted file mode 100644
index 92f6c15..0000000
--- a/arch/arm/include/asm/arch-lpc32xx/clk.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * Copyright (C) 2011 by Vladimir Zapolskiy <vz at mleia.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _LPC32XX_CLK_H
-#define _LPC32XX_CLK_H
-
-#include <asm/types.h>
-
-#define OSC_CLK_FREQUENCY	13000000
-#define RTC_CLK_FREQUENCY	32768
-
-/* Clocking and Power Control Registers */
-struct clk_pm_regs {
-	u32 reserved0[5];
-	u32 boot_map;		/* Boot Map Control Register		*/
-	u32 p0_intr_er;		/* Port 0/1 Start and Interrupt Enable	*/
-	u32 usbdiv_ctrl;	/* USB Clock Pre-Divide Register	*/
-	/* Internal Start Signal Sources Registers	*/
-	u32 start_er_int;	/* Start Enable Register		*/
-	u32 start_rsr_int;	/* Start Raw Status Register		*/
-	u32 start_sr_int;	/* Start Status Register		*/
-	u32 start_apr_int;	/* Start Activation Polarity Register	*/
-	/* Device Pin Start Signal Sources Registers	*/
-	u32 start_er_pin;	/* Start Enable Register		*/
-	u32 start_rsr_pin;	/* Start Raw Status Register		*/
-	u32 start_sr_pin;	/* Start Status Register		*/
-	u32 start_apr_pin;	/* Start Activation Polarity Register	*/
-	/* Clock Control Registers			*/
-	u32 hclkdiv_ctrl;	/* HCLK Divider Control Register	*/
-	u32 pwr_ctrl;		/* Power Control Register		*/
-	u32 pll397_ctrl;	/* PLL397 Control Register		*/
-	u32 osc_ctrl;		/* Main Oscillator Control Register	*/
-	u32 sysclk_ctrl;	/* SYSCLK Control Register		*/
-	u32 lcdclk_ctrl;	/* LCD Clock Control Register		*/
-	u32 hclkpll_ctrl;	/* HCLK PLL Control Register		*/
-	u32 reserved1;
-	u32 adclk_ctrl1;	/* ADC Clock Control1 Register		*/
-	u32 usb_ctrl;		/* USB Control Register			*/
-	u32 sdramclk_ctrl;	/* SDRAM Clock Control Register		*/
-	u32 ddr_lap_nom;	/* DDR Calibration Nominal Value	*/
-	u32 ddr_lap_count;	/* DDR Calibration Measured Value	*/
-	u32 ddr_cal_delay;	/* DDR Calibration Delay Value		*/
-	u32 ssp_ctrl;		/* SSP Control Register			*/
-	u32 i2s_ctrl;		/* I2S Clock Control Register		*/
-	u32 ms_ctrl;		/* Memory Card Control Register		*/
-	u32 reserved2[3];
-	u32 macclk_ctrl;	/* Ethernet MAC Clock Control Register	*/
-	u32 reserved3[4];
-	u32 test_clk;		/* Test Clock Selection Register	*/
-	u32 sw_int;		/* Software Interrupt Register		*/
-	u32 i2cclk_ctrl;	/* I2C Clock Control Register		*/
-	u32 keyclk_ctrl;	/* Keyboard Scan Clock Control Register	*/
-	u32 adclk_ctrl;		/* ADC Clock Control Register		*/
-	u32 pwmclk_ctrl;	/* PWM Clock Control Register		*/
-	u32 timclk_ctrl;	/* Watchdog and Highspeed Timer Control */
-	u32 timclk_ctrl1;	/* Motor and Timer Clock Control	*/
-	u32 spi_ctrl;		/* SPI Control Register			*/
-	u32 flashclk_ctrl;	/* NAND Flash Clock Control Register	*/
-	u32 reserved4;
-	u32 u3clk;		/* UART 3 Clock Control Register	*/
-	u32 u4clk;		/* UART 4 Clock Control Register	*/
-	u32 u5clk;		/* UART 5 Clock Control Register	*/
-	u32 u6clk;		/* UART 6 Clock Control Register	*/
-	u32 irdaclk;		/* IrDA Clock Control Register		*/
-	u32 uartclk_ctrl;	/* UART Clock Control Register		*/
-	u32 dmaclk_ctrl;	/* DMA Clock Control Register		*/
-	u32 autoclk_ctrl;	/* Autoclock Control Register		*/
-};
-
-/* HCLK Divider Control Register bits */
-#define CLK_HCLK_DDRAM_HALF		(0x2 << 7)
-#define CLK_HCLK_DDRAM_NOMINAL		(0x1 << 7)
-#define CLK_HCLK_DDRAM_STOPPED		(0x0 << 7)
-#define CLK_HCLK_PERIPH_DIV_MASK	(0x1F << 2)
-#define CLK_HCLK_PERIPH_DIV(n)		((((n) - 1) & 0x1F) << 2)
-#define CLK_HCLK_ARM_PLL_DIV_MASK	(0x3 << 0)
-#define CLK_HCLK_ARM_PLL_DIV_4		(0x2 << 0)
-#define CLK_HCLK_ARM_PLL_DIV_2		(0x1 << 0)
-#define CLK_HCLK_ARM_PLL_DIV_1		(0x0 << 0)
-
-/* Power Control Register bits */
-#define CLK_PWR_HCLK_RUN_PERIPH		(1 << 10)
-#define CLK_PWR_EMC_SREFREQ		(1 << 9)
-#define CLK_PWR_EMC_SREFREQ_UPDATE	(1 << 8)
-#define CLK_PWR_SDRAM_SREFREQ		(1 << 7)
-#define CLK_PWR_HIGHCORE_LEVEL		(1 << 5)
-#define CLK_PWR_SYSCLKEN_LEVEL		(1 << 4)
-#define CLK_PWR_SYSCLKEN_CTRL		(1 << 3)
-#define CLK_PWR_NORMAL_RUN		(1 << 2)
-#define CLK_PWR_HIGHCORE_CTRL		(1 << 1)
-#define CLK_PWR_STOP_MODE		(1 << 0)
-
-/* SYSCLK Control Register bits */
-#define CLK_SYSCLK_PLL397		(1 << 1)
-#define CLK_SYSCLK_MUX			(1 << 0)
-
-/* HCLK PLL Control Register bits */
-#define CLK_HCLK_PLL_OPERATING		(1 << 16)
-#define CLK_HCLK_PLL_BYPASS		(1 << 15)
-#define CLK_HCLK_PLL_DIRECT		(1 << 14)
-#define CLK_HCLK_PLL_FEEDBACK		(1 << 13)
-#define CLK_HCLK_PLL_POSTDIV_MASK	(0x3 << 11)
-#define CLK_HCLK_PLL_POSTDIV_16		(0x3 << 11)
-#define CLK_HCLK_PLL_POSTDIV_8		(0x2 << 11)
-#define CLK_HCLK_PLL_POSTDIV_4		(0x1 << 11)
-#define CLK_HCLK_PLL_POSTDIV_2		(0x0 << 11)
-#define CLK_HCLK_PLL_PREDIV_MASK	(0x3 << 9)
-#define CLK_HCLK_PLL_PREDIV_4		(0x3 << 9)
-#define CLK_HCLK_PLL_PREDIV_3		(0x2 << 9)
-#define CLK_HCLK_PLL_PREDIV_2		(0x1 << 9)
-#define CLK_HCLK_PLL_PREDIV_1		(0x0 << 9)
-#define CLK_HCLK_PLL_FEEDBACK_DIV_MASK	(0xFF << 1)
-#define CLK_HCLK_PLL_FEEDBACK_DIV(n)	((((n) - 1) & 0xFF) << 1)
-#define CLK_HCLK_PLL_LOCKED		(1 << 0)
-
-/* Ethernet MAC Clock Control Register bits	*/
-#define CLK_MAC_RMII			(0x3 << 3)
-#define CLK_MAC_MII			(0x1 << 3)
-#define CLK_MAC_MASTER			(1 << 2)
-#define CLK_MAC_SLAVE			(1 << 1)
-#define CLK_MAC_REG			(1 << 0)
-
-/* Timer Clock Control1 Register bits */
-#define CLK_TIMCLK_MOTOR		(1 << 6)
-#define CLK_TIMCLK_TIMER3		(1 << 5)
-#define CLK_TIMCLK_TIMER2		(1 << 4)
-#define CLK_TIMCLK_TIMER1		(1 << 3)
-#define CLK_TIMCLK_TIMER0		(1 << 2)
-#define CLK_TIMCLK_TIMER5		(1 << 1)
-#define CLK_TIMCLK_TIMER4		(1 << 0)
-
-/* Timer Clock Control Register bits */
-#define CLK_TIMCLK_HSTIMER		(1 << 1)
-#define CLK_TIMCLK_WATCHDOG		(1 << 0)
-
-/* UART Clock Control Register bits */
-#define CLK_UART(n)			(1 << ((n) - 3))
-
-/* UARTn Clock Select Registers bits */
-#define CLK_UART_HCLK			(1 << 16)
-#define CLK_UART_X_DIV(n)		(((n) & 0xFF) << 8)
-#define CLK_UART_Y_DIV(n)		(((n) & 0xFF) << 0)
-
-/* DMA Clock Control Register bits */
-#define CLK_DMA_ENABLE			(1 << 0)
-
-unsigned int get_sys_clk_rate(void);
-unsigned int get_hclk_pll_rate(void);
-unsigned int get_hclk_clk_div(void);
-unsigned int get_hclk_clk_rate(void);
-unsigned int get_periph_clk_div(void);
-unsigned int get_periph_clk_rate(void);
-
-#endif /* _LPC32XX_CLK_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h
deleted file mode 100644
index 8f6426b..0000000
--- a/arch/arm/include/asm/arch-lpc32xx/config.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Common definitions for LPC32XX board configurations
- *
- * Copyright (C) 2011 Vladimir Zapolskiy <vz at mleia.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _LPC32XX_CONFIG_H
-#define _LPC32XX_CONFIG_H
-
-/* Basic CPU architecture */
-#define CONFIG_ARCH_CPU_INIT
-
-#define CONFIG_NR_DRAM_BANKS_MAX	2
-
-/* UART configuration */
-#if (CONFIG_SYS_LPC32XX_UART >= 3) && (CONFIG_SYS_LPC32XX_UART <= 6)
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_CONS_INDEX		(CONFIG_SYS_LPC32XX_UART - 2)
-#elif	(CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \
-	(CONFIG_SYS_LPC32XX_UART == 7)
-#define CONFIG_LPC32XX_HSUART
-#else
-#error "define CONFIG_SYS_LPC32XX_UART in the range from 1 to 7"
-#endif
-
-#if defined(CONFIG_SYS_NS16550_SERIAL)
-#define CONFIG_SYS_NS16550
-
-#define CONFIG_SYS_NS16550_REG_SIZE	-4
-#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
-
-#define CONFIG_SYS_NS16550_COM1		UART3_BASE
-#define CONFIG_SYS_NS16550_COM2		UART4_BASE
-#define CONFIG_SYS_NS16550_COM3		UART5_BASE
-#define CONFIG_SYS_NS16550_COM4		UART6_BASE
-#endif
-
-#if defined(CONFIG_LPC32XX_HSUART)
-#if	CONFIG_SYS_LPC32XX_UART == 1
-#define HS_UART_BASE			HS_UART1_BASE
-#elif	CONFIG_SYS_LPC32XX_UART == 2
-#define HS_UART_BASE			HS_UART2_BASE
-#else	/* CONFIG_SYS_LPC32XX_UART == 7 */
-#define HS_UART_BASE			HS_UART7_BASE
-#endif
-#endif
-
-#define CONFIG_SYS_BAUDRATE_TABLE	\
-		{ 9600, 19200, 38400, 57600, 115200, 230400, 460800 }
-
-/* NOR Flash */
-#if defined(CONFIG_SYS_FLASH_CFI)
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_PROTECTION
-#endif
-
-#endif /* _LPC32XX_CONFIG_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/cpu.h b/arch/arm/include/asm/arch-lpc32xx/cpu.h
deleted file mode 100644
index 199b4a0..0000000
--- a/arch/arm/include/asm/arch-lpc32xx/cpu.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (C) 2011 by Vladimir Zapolskiy <vz at mleia.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _LPC32XX_CPU_H
-#define _LPC32XX_CPU_H
-
-/* LPC32XX Memory map */
-
-/* AHB physical base addresses */
-#define SLC_NAND_BASE	0x20020000	/* SLC NAND Flash registers base    */
-#define SSP0_BASE	0x20084000	/* SSP0 registers base              */
-#define SD_CARD_BASE	0x20098000	/* SD card interface registers base */
-#define MLC_NAND_BASE	0x200A8000	/* MLC NAND Flash registers base    */
-#define DMA_BASE	0x31000000	/* DMA controller registers base    */
-#define USB_BASE	0x31020000	/* USB registers base               */
-#define LCD_BASE	0x31040000	/* LCD registers base               */
-#define ETHERNET_BASE	0x31060000	/* Ethernet registers base          */
-#define EMC_BASE	0x31080000	/* EMC configuration registers base */
-
-/* FAB peripherals base addresses */
-#define CLK_PM_BASE	0x40004000	/* System control registers base    */
-#define HS_UART1_BASE	0x40014000	/* High speed UART 1 registers base */
-#define HS_UART2_BASE	0x40018000	/* High speed UART 2 registers base */
-#define HS_UART7_BASE	0x4001C000	/* High speed UART 7 registers base */
-#define RTC_BASE	0x40024000	/* RTC registers base               */
-#define GPIO_BASE	0x40028000	/* GPIO registers base              */
-#define WDT_BASE	0x4003C000	/* Watchdog timer registers base    */
-#define TIMER0_BASE	0x40044000	/* Timer0 registers base            */
-#define TIMER1_BASE	0x4004C000	/* Timer1 registers base            */
-#define UART_CTRL_BASE	0x40054000	/* UART control regsisters base     */
-
-/* APB peripherals base addresses */
-#define UART3_BASE	0x40080000	/* UART 3 registers base            */
-#define UART4_BASE	0x40088000	/* UART 4 registers base            */
-#define UART5_BASE	0x40090000	/* UART 5 registers base            */
-#define UART6_BASE	0x40098000	/* UART 6 registers base            */
-
-/* External SDRAM Memory Bank base addresses */
-#define EMC_DYCS0_BASE	0x80000000	/* SDRAM DYCS0 base address         */
-#define EMC_DYCS1_BASE	0xA0000000	/* SDRAM DYCS1 base address         */
-
-/* External Static Memory Bank base addresses */
-#define EMC_CS0_BASE	0xE0000000
-#define EMC_CS1_BASE	0xE1000000
-#define EMC_CS2_BASE	0xE2000000
-#define EMC_CS3_BASE	0xE3000000
-
-#endif /* _LPC32XX_CPU_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/emc.h b/arch/arm/include/asm/arch-lpc32xx/emc.h
deleted file mode 100644
index 82d9bcc..0000000
--- a/arch/arm/include/asm/arch-lpc32xx/emc.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * Copyright (C) 2011 by Vladimir Zapolskiy <vz at mleia.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _LPC32XX_EMC_H
-#define _LPC32XX_EMC_H
-
-#include <asm/types.h>
-
-/* EMC Registers */
-struct emc_regs {
-	u32 ctrl;		/* Controls operation of the EMC             */
-	u32 status;		/* Provides EMC status information           */
-	u32 config;		/* Configures operation of the EMC           */
-	u32 reserved0[5];
-	u32 control;		/* Controls dyn memory operation             */
-	u32 refresh;		/* Configures dyn memory refresh operation   */
-	u32 read_config;	/* Configures the dyn memory read strategy   */
-	u32 reserved1;
-	u32 t_rp;		/* Precharge command period                  */
-	u32 t_ras;		/* Active to precharge command period        */
-	u32 t_srex;		/* Self-refresh exit time                    */
-	u32 reserved2[2];
-	u32 t_wr;		/* Write recovery time                       */
-	u32 t_rc;		/* Active to active command period           */
-	u32 t_rfc;		/* Auto-refresh period                       */
-	u32 t_xsr;		/* Exit self-refresh to active command time  */
-	u32 t_rrd;		/* Active bank A to active bank B latency    */
-	u32 t_mrd;		/* Load mode register to active command time */
-	u32 t_cdlr;		/* Last data in to read command time         */
-	u32 reserved3[8];
-	u32 extended_wait;	/* time for static memory rd/wr transfers    */
-	u32 reserved4[31];
-	u32 config0;		/* Configuration information for the SDRAM   */
-	u32 rascas0;		/* RAS and CAS latencies for the SDRAM       */
-	u32 reserved5[6];
-	u32 config1;		/* Configuration information for the SDRAM   */
-	u32 rascas1;		/* RAS and CAS latencies for the SDRAM       */
-	u32 reserved6[54];
-	struct emc_stat_t {
-		u32 config;	/* Static memory configuration               */
-		u32 waitwen;	/* Delay from chip select to write enable    */
-		u32 waitoen;	/* Delay to output enable                    */
-		u32 waitrd;	/* Delay to a read access                    */
-		u32 waitpage;	/* Delay for async page mode read            */
-		u32 waitwr;	/* Delay to a write access                   */
-		u32 waitturn;	/* Number of bus turnaround cycles           */
-		u32 reserved;
-	} stat[4];
-	u32 reserved7[96];
-	struct emc_ahb_t {
-		u32 control;	/* Control register for AHB                  */
-		u32 status;	/* Status register for AHB                   */
-		u32 timeout;	/* Timeout register for AHB                  */
-		u32 reserved[5];
-	} ahb[5];
-};
-
-/* Static Memory Configuration Register bits */
-#define EMC_STAT_CONFIG_WP		(1 << 20)
-#define EMC_STAT_CONFIG_EW		(1 << 8)
-#define EMC_STAT_CONFIG_PB		(1 << 7)
-#define EMC_STAT_CONFIG_PC		(1 << 6)
-#define EMC_STAT_CONFIG_PM		(1 << 3)
-#define EMC_STAT_CONFIG_32BIT		(2 << 0)
-#define EMC_STAT_CONFIG_16BIT		(1 << 0)
-#define EMC_STAT_CONFIG_8BIT		(0 << 0)
-
-/* Static Memory Delay Registers */
-#define EMC_STAT_WAITWEN(n)		(((n) - 1) & 0x0F)
-#define EMC_STAT_WAITOEN(n)		(((n) - 1) & 0x0F)
-#define EMC_STAT_WAITRD(n)		(((n) - 1) & 0x1F)
-#define EMC_STAT_WAITPAGE(n)		(((n) - 1) & 0x1F)
-#define EMC_STAT_WAITWR(n)		(((n) - 2) & 0x1F)
-#define EMC_STAT_WAITTURN(n)		(((n) - 1) & 0x0F)
-
-#endif /* _LPC32XX_EMC_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
deleted file mode 100644
index 28812be..0000000
--- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * Copyright (C) 2011 Vladimir Zapolskiy <vz at mleia.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _LPC32XX_SYS_PROTO_H
-#define _LPC32XX_SYS_PROTO_H
-
-void lpc32xx_uart_init(unsigned int uart_id);
-
-#endif /* _LPC32XX_SYS_PROTO_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/timer.h b/arch/arm/include/asm/arch-lpc32xx/timer.h
deleted file mode 100644
index bd90144..0000000
--- a/arch/arm/include/asm/arch-lpc32xx/timer.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Copyright (C) 2011 by Vladimir Zapolskiy <vz at mleia.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _LPC32XX_TIMER_H
-#define _LPC32XX_TIMER_H
-
-#include <asm/types.h>
-
-/* Timer/Counter Registers */
-struct timer_regs {
-	u32 ir;			/* Interrupt Register		*/
-	u32 tcr;		/* Timer Control Register	*/
-	u32 tc;			/* Timer Counter		*/
-	u32 pr;			/* Prescale Register		*/
-	u32 pc;			/* Prescale Counter		*/
-	u32 mcr;		/* Match Control Register	*/
-	u32 mr[4];		/* Match Registers		*/
-	u32 ccr;		/* Capture Control Register	*/
-	u32 cr[4];		/* Capture Registers		*/
-	u32 emr;		/* External Match Register	*/
-	u32 reserved[12];
-	u32 ctcr;		/* Count Control Register	*/
-};
-
-/* Timer/Counter Interrupt Register bits */
-#define TIMER_IR_CR(n)			(1 << ((n) + 4))
-#define TIMER_IR_MR(n)			(1 << (n))
-
-/* Timer/Counter Timer Control Register bits */
-#define TIMER_TCR_COUNTER_RESET		(1 << 1)
-#define TIMER_TCR_COUNTER_ENABLE	(1 << 0)
-#define TIMER_TCR_COUNTER_DISABLE	(0 << 0)
-
-/* Timer/Counter Match Control Register bits */
-#define TIMER_MCR_STOP(n)		(1 << (3 * (n) + 2))
-#define TIMER_MCR_RESET(n)		(1 << (3 * (n) + 1))
-#define TIMER_MCR_INTERRUPT(n)		(1 << (3 * (n)))
-
-/* Timer/Counter Capture Control Register bits */
-#define TIMER_CCR_INTERRUPT(n)		(1 << (3 * (n) + 2))
-#define TIMER_CCR_FALLING_EDGE(n)	(1 << (3 * (n) + 1))
-#define TIMER_CCR_RISING_EDGE(n)	(1 << (3 * (n)))
-
-/* Timer/Counter External Match Register bits */
-#define TIMER_EMR_EMC_TOGGLE(n)		(0x3 << (2 * (n) + 4))
-#define TIMER_EMR_EMC_SET(n)		(0x2 << (2 * (n) + 4))
-#define TIMER_EMR_EMC_CLEAR(n)		(0x1 << (2 * (n) + 4))
-#define TIMER_EMR_EMC_NOTHING(n)	(0x0 << (2 * (n) + 4))
-#define TIMER_EMR_EM(n)			(1 << (n))
-
-/* Timer/Counter Count Control Register bits */
-#define TIMER_CTCR_INPUT(n)		((n) << 2)
-#define TIMER_CTCR_MODE_COUNTER_BOTH	(0x3 << 0)
-#define TIMER_CTCR_MODE_COUNTER_FALLING	(0x2 << 0)
-#define TIMER_CTCR_MODE_COUNTER_RISING	(0x1 << 0)
-#define TIMER_CTCR_MODE_TIMER		(0x0 << 0)
-
-#endif /* _LPC32XX_TIMER_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/uart.h b/arch/arm/include/asm/arch-lpc32xx/uart.h
deleted file mode 100644
index 01dacd6..0000000
--- a/arch/arm/include/asm/arch-lpc32xx/uart.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * Copyright (C) 2011 by Vladimir Zapolskiy <vz at mleia.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _LPC32XX_UART_H
-#define _LPC32XX_UART_H
-
-#include <asm/types.h>
-
-/* 14-clock UART Registers */
-struct hsuart_regs {
-	union {
-		u32 rx;		/* Receiver FIFO		*/
-		u32 tx;		/* Transmitter FIFO		*/
-	};
-	u32 level;		/* FIFO Level Register		*/
-	u32 iir;		/* Interrupt ID Register	*/
-	u32 ctrl;		/* Control Register		*/
-	u32 rate;		/* Rate Control Register	*/
-};
-
-/* 14-clock UART Receiver FIFO Register bits */
-#define HSUART_RX_BREAK			(1 << 10)
-#define HSUART_RX_ERROR			(1 << 9)
-#define HSUART_RX_EMPTY			(1 << 8)
-#define HSUART_RX_DATA			(0xff << 0)
-
-/* 14-clock UART Level Register bits */
-#define HSUART_LEVEL_TX			(0xff << 8)
-#define HSUART_LEVEL_RX			(0xff << 0)
-
-/* 14-clock UART Interrupt Identification Register bits */
-#define HSUART_IIR_TX_INT_SET		(1 << 6)
-#define HSUART_IIR_RX_OE		(1 << 5)
-#define HSUART_IIR_BRK			(1 << 4)
-#define HSUART_IIR_FE			(1 << 3)
-#define HSUART_IIR_RX_TIMEOUT		(1 << 2)
-#define HSUART_IIR_RX_TRIG		(1 << 1)
-#define HSUART_IIR_TX			(1 << 0)
-
-/* 14-clock UART Control Register bits */
-#define HSUART_CTRL_HRTS_INV		(1 << 21)
-#define HSUART_CTRL_HRTS_TRIG_48	(0x3 << 19)
-#define HSUART_CTRL_HRTS_TRIG_32	(0x2 << 19)
-#define HSUART_CTRL_HRTS_TRIG_16	(0x1 << 19)
-#define HSUART_CTRL_HRTS_TRIG_8		(0x0 << 19)
-#define HSUART_CTRL_HRTS_EN		(1 << 18)
-#define HSUART_CTRL_TMO_16		(0x3 << 16)
-#define HSUART_CTRL_TMO_8		(0x2 << 16)
-#define HSUART_CTRL_TMO_4		(0x1 << 16)
-#define HSUART_CTRL_TMO_DISABLED	(0x0 << 16)
-#define HSUART_CTRL_HCTS_INV		(1 << 15)
-#define HSUART_CTRL_HCTS_EN		(1 << 14)
-#define HSUART_CTRL_HSU_OFFSET(n)	((n) << 9)
-#define HSUART_CTRL_HSU_BREAK		(1 << 8)
-#define HSUART_CTRL_HSU_ERR_INT_EN	(1 << 7)
-#define HSUART_CTRL_HSU_RX_INT_EN	(1 << 6)
-#define HSUART_CTRL_HSU_TX_INT_EN	(1 << 5)
-#define HSUART_CTRL_HSU_RX_TRIG_48	(0x5 << 2)
-#define HSUART_CTRL_HSU_RX_TRIG_32	(0x4 << 2)
-#define HSUART_CTRL_HSU_RX_TRIG_16	(0x3 << 2)
-#define HSUART_CTRL_HSU_RX_TRIG_8	(0x2 << 2)
-#define HSUART_CTRL_HSU_RX_TRIG_4	(0x1 << 2)
-#define HSUART_CTRL_HSU_RX_TRIG_1	(0x0 << 2)
-#define HSUART_CTRL_HSU_TX_TRIG_16	(0x3 << 0)
-#define HSUART_CTRL_HSU_TX_TRIG_8	(0x2 << 0)
-#define HSUART_CTRL_HSU_TX_TRIG_4	(0x1 << 0)
-#define HSUART_CTRL_HSU_TX_TRIG_0	(0x0 << 0)
-
-/* UART Control Registers */
-struct uart_ctrl_regs {
-	u32 ctrl;		/* Control Register		*/
-	u32 clkmode;		/* Clock Mode Register		*/
-	u32 loop;		/* Loopback Control Register	*/
-};
-
-/* UART Control Register bits */
-#define UART_CTRL_UART3_MD_CTRL		(1 << 11)
-#define UART_CTRL_HDPX_INV		(1 << 10)
-#define UART_CTRL_HDPX_EN		(1 << 9)
-#define UART_CTRL_UART6_IRDA		(1 << 5)
-#define UART_CTRL_IR_TX6_INV		(1 << 4)
-#define UART_CTRL_IR_RX6_INV		(1 << 3)
-#define UART_CTRL_IR_RX_LENGTH		(1 << 2)
-#define UART_CTRL_IR_TX_LENGTH		(1 << 1)
-#define UART_CTRL_UART5_USB_MODE	(1 << 0)
-
-/* UART Clock Mode Register bits */
-#define UART_CLKMODE_STATX(n)		(1 << ((n) + 16))
-#define UART_CLKMODE_STAT		(1 << 14)
-#define UART_CLKMODE_MASK(n)		(0x3 << (2 * (n) - 2))
-#define UART_CLKMODE_AUTO(n)		(0x2 << (2 * (n) - 2))
-#define UART_CLKMODE_ON(n)		(0x1 << (2 * (n) - 2))
-#define UART_CLKMODE_OFF(n)		(0x0 << (2 * (n) - 2))
-
-/* UART Loopback Control Register bits */
-#define UART_LOOPBACK(n)		(1 << ((n) - 1))
-
-#endif /* _LPC32XX_UART_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/wdt.h b/arch/arm/include/asm/arch-lpc32xx/wdt.h
deleted file mode 100644
index d7903c2..0000000
--- a/arch/arm/include/asm/arch-lpc32xx/wdt.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright (C) 2011 by Vladimir Zapolskiy <vz at mleia.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _LPC32XX_WDT_H
-#define _LPC32XX_WDT_H
-
-#include <asm/types.h>
-
-/* Watchdog Timer Registers */
-struct wdt_regs {
-	u32 isr;		/* Interrupt Status Register		*/
-	u32 ctrl;		/* Control Register			*/
-	u32 counter;		/* Counter Value Register		*/
-	u32 mctrl;		/* Match Control Register		*/
-	u32 match0;		/* Match 0 Register			*/
-	u32 emr;		/* External Match Control Register	*/
-	u32 pulse;		/* Reset Pulse Length Register		*/
-	u32 res;		/* Reset Source Register		*/
-};
-
-/* Watchdog Timer Control Register bits */
-#define WDTIM_CTRL_PAUSE_EN		(1 << 2)
-#define WDTIM_CTRL_RESET_COUNT		(1 << 1)
-#define WDTIM_CTRL_COUNT_ENAB		(1 << 0)
-
-/* Watchdog Timer Match Control Register bits */
-#define WDTIM_MCTRL_RESFRC2		(1 << 6)
-#define WDTIM_MCTRL_RESFRC1		(1 << 5)
-#define WDTIM_MCTRL_M_RES2		(1 << 4)
-#define WDTIM_MCTRL_M_RES1		(1 << 3)
-#define WDTIM_MCTRL_STOP_COUNT0		(1 << 2)
-#define WDTIM_MCTRL_RESET_COUNT0	(1 << 1)
-#define WDTIM_MCTRL_MR0_INT		(1 << 0)
-
-#endif /* _LPC32XX_WDT_H */
diff --git a/board/timll/devkit3250/Kconfig b/board/timll/devkit3250/Kconfig
deleted file mode 100644
index e3bd456..0000000
--- a/board/timll/devkit3250/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_DEVKIT3250
-
-config SYS_BOARD
-	default "devkit3250"
-
-config SYS_VENDOR
-	default "timll"
-
-config SYS_SOC
-	default "lpc32xx"
-
-config SYS_CONFIG_NAME
-	default "devkit3250"
-
-endif
diff --git a/board/timll/devkit3250/MAINTAINERS b/board/timll/devkit3250/MAINTAINERS
deleted file mode 100644
index cb93563..0000000
--- a/board/timll/devkit3250/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-DEVKIT3250 BOARD
-M:	Vladimir Zapolskiy <vz at mleia.com>
-S:	Maintained
-F:	board/timll/devkit3250/
-F:	include/configs/devkit3250.h
-F:	configs/devkit3250_defconfig
diff --git a/board/timll/devkit3250/Makefile b/board/timll/devkit3250/Makefile
deleted file mode 100644
index 4722986..0000000
--- a/board/timll/devkit3250/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Copyright (C) 2011 by Vladimir Zapolskiy <vz at mleia.com>
-# Copyright (C) 2008, Guennadi Liakhovetski <lg at denx.de>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= devkit3250.o
diff --git a/board/timll/devkit3250/devkit3250.c b/board/timll/devkit3250/devkit3250.c
deleted file mode 100644
index 6acc416..0000000
--- a/board/timll/devkit3250/devkit3250.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Embest/Timll DevKit3250 board support
- *
- * Copyright (C) 2011 Vladimir Zapolskiy <vz at mleia.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/emc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct emc_regs *emc = (struct emc_regs *)EMC_BASE;
-
-int board_early_init_f(void)
-{
-	lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
-
-	return 0;
-}
-
-int board_init(void)
-{
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params  = CONFIG_SYS_SDRAM_BASE + 0x100;
-
-#ifdef CONFIG_SYS_FLASH_CFI
-	/* Use 16-bit memory interface for NOR Flash */
-	emc->stat[0].config	= EMC_STAT_CONFIG_PB | EMC_STAT_CONFIG_16BIT;
-
-	/* Change the NOR timings to optimum value to get maximum bandwidth */
-	emc->stat[0].waitwen	= EMC_STAT_WAITWEN(1);
-	emc->stat[0].waitoen	= EMC_STAT_WAITOEN(1);
-	emc->stat[0].waitrd	= EMC_STAT_WAITRD(12);
-	emc->stat[0].waitpage	= EMC_STAT_WAITPAGE(12);
-	emc->stat[0].waitwr	= EMC_STAT_WAITWR(5);
-	emc->stat[0].waitturn	= EMC_STAT_WAITTURN(2);
-#endif
-
-	return 0;
-}
-
-int dram_init(void)
-{
-	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
-				    CONFIG_SYS_SDRAM_SIZE);
-
-	return 0;
-}
diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig
deleted file mode 100644
index ba990bc..0000000
--- a/configs/devkit3250_defconfig
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_DEVKIT3250=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index b24bfea..649d4d0 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
 
 Board            Arch        CPU            Commit      Removed     Last known maintainer/contact
 =================================================================================================
+devkit3250       arm         arm926ejs      -           -           Vladimir Zapolskiy <vz at mleia.com>
 zmx25            arm         arm926ejs      -           -           Matthias Weisser <weisserm at arcor.de>
 jadecpu          arm         arm926ejs      -           -           Matthias Weisser <weisserm at arcor.de>
 imx31_phycore    arm         arm1136        -           -           Guennadi Liakhovetski <g.liakhovetski at gmx.de>
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 4cc00cd..cedf246 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -20,7 +20,6 @@ obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
 obj-$(CONFIG_ARM_DCC) += arm_dcc.o
 obj-$(CONFIG_ATMEL_USART) += atmel_usart.o
 obj-$(CONFIG_DW_SERIAL) += serial_dw.o
-obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o
 obj-$(CONFIG_MCFUART) += mcfuart.o
 obj-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o
 obj-$(CONFIG_SYS_NS16550) += ns16550.o
diff --git a/drivers/serial/lpc32xx_hsuart.c b/drivers/serial/lpc32xx_hsuart.c
deleted file mode 100644
index c8926a8..0000000
--- a/drivers/serial/lpc32xx_hsuart.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * Copyright (C) 2011 Vladimir Zapolskiy <vz at mleia.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/uart.h>
-#include <asm/io.h>
-#include <serial.h>
-#include <linux/compiler.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct hsuart_regs *hsuart = (struct hsuart_regs *)HS_UART_BASE;
-
-static void lpc32xx_serial_setbrg(void)
-{
-	u32 div;
-
-	/* UART rate = PERIPH_CLK / ((HSU_RATE + 1) x 14) */
-	div = (get_serial_clock() / 14 + gd->baudrate / 2) / gd->baudrate - 1;
-	if (div > 255)
-		div = 255;
-
-	writel(div, &hsuart->rate);
-}
-
-static int lpc32xx_serial_getc(void)
-{
-	while (!(readl(&hsuart->level) & HSUART_LEVEL_RX))
-		/* NOP */;
-
-	return readl(&hsuart->rx) & HSUART_RX_DATA;
-}
-
-static void lpc32xx_serial_putc(const char c)
-{
-	if (c == '\n')
-		serial_putc('\r');
-
-	writel(c, &hsuart->tx);
-
-	/* Wait for character to be sent */
-	while (readl(&hsuart->level) & HSUART_LEVEL_TX)
-		/* NOP */;
-}
-
-static int lpc32xx_serial_tstc(void)
-{
-	if (readl(&hsuart->level) & HSUART_LEVEL_RX)
-		return 1;
-
-	return 0;
-}
-
-static int lpc32xx_serial_init(void)
-{
-	lpc32xx_serial_setbrg();
-
-	/* Disable hardware RTS and CTS flow control, set up RX and TX FIFO */
-	writel(HSUART_CTRL_TMO_16 | HSUART_CTRL_HSU_OFFSET(20) |
-	       HSUART_CTRL_HSU_RX_TRIG_32 | HSUART_CTRL_HSU_TX_TRIG_0,
-	       &hsuart->ctrl);
-	return 0;
-}
-
-static struct serial_device lpc32xx_serial_drv = {
-	.name	= "lpc32xx_serial",
-	.start	= lpc32xx_serial_init,
-	.stop	= NULL,
-	.setbrg	= lpc32xx_serial_setbrg,
-	.putc	= lpc32xx_serial_putc,
-	.puts	= default_serial_puts,
-	.getc	= lpc32xx_serial_getc,
-	.tstc	= lpc32xx_serial_tstc,
-};
-
-void lpc32xx_serial_initialize(void)
-{
-	serial_register(&lpc32xx_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
-	return &lpc32xx_serial_drv;
-}
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index 95c992a..3210a26 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -131,7 +131,6 @@ serial_initfunc(ks8695_serial_initialize);
 serial_initfunc(leon2_serial_initialize);
 serial_initfunc(leon3_serial_initialize);
 serial_initfunc(lh7a40x_serial_initialize);
-serial_initfunc(lpc32xx_serial_initialize);
 serial_initfunc(marvell_serial_initialize);
 serial_initfunc(max3100_serial_initialize);
 serial_initfunc(mcf_serial_initialize);
@@ -224,7 +223,6 @@ void serial_initialize(void)
 	leon2_serial_initialize();
 	leon3_serial_initialize();
 	lh7a40x_serial_initialize();
-	lpc32xx_serial_initialize();
 	marvell_serial_initialize();
 	max3100_serial_initialize();
 	mcf_serial_initialize();
diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h
deleted file mode 100644
index bd96a7d..0000000
--- a/include/configs/devkit3250.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * Embest/Timll DevKit3250 board configuration file
- *
- * Copyright (C) 2011 Vladimir Zapolskiy <vz at mleia.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_DEVKIT3250_H__
-#define __CONFIG_DEVKIT3250_H__
-
-/* SoC and board defines */
-#include <linux/sizes.h>
-#include <asm/arch/cpu.h>
-
-/*
- * Define DevKit3250 machine type by hand until it lands in mach-types
- */
-#define MACH_TYPE_DEVKIT3250		3697
-#define CONFIG_MACH_TYPE		MACH_TYPE_DEVKIT3250
-
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_BOARD_EARLY_INIT_F
-
-/*
- * Memory configurations
- */
-#define CONFIG_NR_DRAM_BANKS		1
-#define CONFIG_SYS_MALLOC_LEN		SZ_1M
-#define CONFIG_SYS_SDRAM_BASE		EMC_DYCS0_BASE
-#define CONFIG_SYS_SDRAM_SIZE		SZ_64M
-#define CONFIG_SYS_TEXT_BASE		0x83FA0000
-#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE + SZ_32K)
-#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_TEXT_BASE - SZ_1M)
-
-#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_32K)
-
-#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_4K \
-					 - GENERATED_GBL_DATA_SIZE)
-
-/*
- * Serial Driver
- */
-#define CONFIG_SYS_LPC32XX_UART		2   /* UART2 */
-#define CONFIG_BAUDRATE			115200
-
-/*
- * NOR Flash
- */
-#define CONFIG_CMD_FLASH
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT	71
-#define CONFIG_SYS_FLASH_BASE		EMC_CS0_BASE
-#define CONFIG_SYS_FLASH_SIZE		SZ_4M
-#define CONFIG_SYS_FLASH_CFI
-
-/*
- * U-Boot General Configurations
- */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_CBSIZE		1024
-#define CONFIG_SYS_PBSIZE		\
-	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS		16
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
-
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_SIZE			SZ_128K
-
-/*
- * U-Boot Commands
- */
-#include <config_cmd_default.h>
-#define CONFIG_CMD_CACHE
-
-/*
- * Boot Linux
- */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_BOOTDELAY		3
-
-#define CONFIG_BOOTFILE			"uImage"
-#define CONFIG_BOOTARGS			"console=ttyS2,115200n8"
-#define CONFIG_LOADADDR			0x80008000
-
-/*
- * Include SoC specific configuration
- */
-#include <asm/arch/config.h>
-
-#endif  /* __CONFIG_DEVKIT3250_H__*/
diff --git a/include/serial.h b/include/serial.h
index 3d2e569..42e2cc1 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -186,7 +186,6 @@ void ks8695_serial_initialize(void);
 void leon2_serial_initialize(void);
 void leon3_serial_initialize(void);
 void lh7a40x_serial_initialize(void);
-void lpc32xx_serial_initialize(void);
 void marvell_serial_initialize(void);
 void max3100_serial_initialize(void);
 void mcf_serial_initialize(void);
-- 
1.9.1




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