[U-Boot] [PATCH 1/2] arm: ls102xa: Add silicon version detection for QDS and TWR boards
Alison Wang
b18965 at freescale.com
Fri Feb 13 06:08:14 CET 2015
For LS102xA, some workarounds are only used in VER1.0, so silicon
version detection are added for QDS and TWR boards.
Signed-off-by: Alison Wang <alison.wang at freescale.com>
---
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 3 +
board/freescale/ls1021aqds/ls1021aqds.c | 69 ++++++++++++++++-------
board/freescale/ls1021atwr/ls1021atwr.c | 19 +++++--
3 files changed, 64 insertions(+), 27 deletions(-)
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index f70d568..4b1cd3b 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -17,6 +17,9 @@
#define SOC_VER_LS1021 0x11
#define SOC_VER_LS1022 0x12
+#define SOC_VER_1_0 0x1
+#define SOC_VER_2_0 0x2
+
#define CCSR_BRR_OFFSET 0xe4
#define CCSR_SCRATCHRW1_OFFSET 0x200
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index 20eade4..b6bba6c 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -181,6 +181,11 @@ int board_early_init_f(void)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ unsigned int svr, major;
+
+ svr = in_be32(&gur->svr);
+ major = SVR_MAJ(svr);
#ifdef CONFIG_TSEC_ENET
out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
@@ -205,19 +210,21 @@ int board_early_init_f(void)
out_le32(&cci->slave[4].snoop_ctrl,
CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
- /*
- * Set CCI-400 Slave interface S1, S2 Shareable Override Register
- * All transactions are treated as non-shareable
- */
- out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
- out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
-
- /* Workaround for the issue that DDR could not respond to
- * barrier transaction which is generated by executing DSB/ISB
- * instruction. Set CCI-400 control override register to
- * terminate the barrier transaction. After DDR is initialized,
- * allow barrier transaction to DDR again */
- out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
+ if (major == SOC_VER_1_0) {
+ /*
+ * Set CCI-400 Slave interface S1, S2 Shareable Override
+ * Register All transactions are treated as non-shareable
+ */
+ out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+ out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+
+ /* Workaround for the issue that DDR could not respond to
+ * barrier transaction which is generated by executing DSB/ISB
+ * instruction. Set CCI-400 control override register to
+ * terminate the barrier transaction. After DDR is initialized,
+ * allow barrier transaction to DDR again */
+ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
+ }
#if defined(CONFIG_DEEP_SLEEP)
if (is_warm_boot())
@@ -231,9 +238,10 @@ int board_early_init_f(void)
void board_init_f(ulong dummy)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ unsigned int svr, major;
#ifdef CONFIG_NAND_BOOT
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
u32 porsr1, pinctl;
/*
@@ -267,7 +275,12 @@ void board_init_f(ulong dummy)
#ifdef CONFIG_SPL_I2C_SUPPORT
i2c_init_all();
#endif
- out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
+
+ svr = in_be32(&gur->svr);
+ major = SVR_MAJ(svr);
+
+ if (major == SOC_VER_1_0)
+ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
dram_init();
@@ -529,10 +542,17 @@ struct smmu_stream_id dev_stream_id[] = {
int board_init(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ unsigned int svr, major;
+
+ svr = in_be32(&gur->svr);
+ major = SVR_MAJ(svr);
- /* Set CCI-400 control override register to
- * enable barrier transaction */
- out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+ if (major == SOC_VER_1_0) {
+ /* Set CCI-400 control override register to
+ * enable barrier transaction */
+ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+ }
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
@@ -559,10 +579,17 @@ int board_init(void)
void board_sleep_prepare(void)
{
struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
+ unsigned int svr, major;
+
+ svr = in_be32(&gur->svr);
+ major = SVR_MAJ(svr);
+
+ if (major == SOC_VER_1_0) {
+ /* Set CCI-400 control override register to
+ * enable barrier transaction */
+ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+ }
- /* Set CCI-400 control override register to
- * enable barrier transaction */
- out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
#ifdef CONFIG_LS102XA_NS_ACCESS
enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index bc8b006..bd6068f 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -264,6 +264,11 @@ int board_early_init_f(void)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ unsigned int svr, major;
+
+ svr = in_be32(&gur->svr);
+ major = SVR_MAJ(svr);
#ifdef CONFIG_TSEC_ENET
out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
@@ -289,12 +294,14 @@ int board_early_init_f(void)
out_le32(&cci->slave[4].snoop_ctrl,
CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
- /*
- * Set CCI-400 Slave interface S1, S2 Shareable Override Register
- * All transactions are treated as non-shareable
- */
- out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
- out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+ if (major == SOC_VER_1_0) {
+ /*
+ * Set CCI-400 Slave interface S1, S2 Shareable Override
+ * Register All transactions are treated as non-shareable
+ */
+ out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+ out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+ }
return 0;
}
--
2.1.0.27.g96db324
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