[U-Boot] [PATCH 0/3] ARM: DRA7: DDR3: Update timings and leveling parameters

Lokesh Vutla lokeshvutla at ti.com
Mon Feb 16 05:45:54 CET 2015


This series updates the DDR timing and leveling parameters on DRA7 and DRA72
EVM.

Angela Stegmaier (1):
  ARM: DRA72x: DDR3: Fix EMIF timings for 666MHz clock

Lokesh Vutla (2):
  ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register value
  ARM: DRA7-evm: DDR3: Update leveling values

 arch/arm/cpu/armv7/omap-common/emif-common.c |  4 +-
 arch/arm/cpu/armv7/omap5/sdram.c             | 83 ++++++++++++++--------------
 arch/arm/include/asm/emif.h                  |  1 +
 board/ti/beagle_x15/board.c                  |  6 +-
 4 files changed, 51 insertions(+), 43 deletions(-)

-- 
1.9.1



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