[U-Boot] [PATCH v2 2/4] mmc: fsl_esdhc: Add support to force VSELECT set

[Otavio Salvador]

Some boards cannot do voltage negotiation but need to set the VSELECT
bit forcely to ensure it to work at 1.8V.

This commit adds CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT flag for this use.

Signed-off-by: Otavio Salvador <otavio at ossystems.com.br>
---

Changes in v2: None

 doc/README.fsl-esdhc    | 1 +
 drivers/mmc/fsl_esdhc.c | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/doc/README.fsl-esdhc b/doc/README.fsl-esdhc
index b70f271..619c6b2 100644
--- a/doc/README.fsl-esdhc
+++ b/doc/README.fsl-esdhc
@@ -1,5 +1,6 @@
 CONFIG_SYS_FSL_ESDHC_LE means ESDHC IP is in little-endian mode.
 CONFIG_SYS_FSL_ESDHC_BE means ESDHC IP is in big-endian mode.
+CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT forces to run at 1.8V.
 
 Accessing ESDHC registers can be determined by ESDHC IP's endian
 mode or processor's endian mode.
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 6a3e147..67ee179 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -523,6 +523,10 @@ static int esdhc_init(struct mmc *mmc)
 	/* Set timout to the maximum value */
 	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
 
+#ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
+	esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
+#endif
+
 	return 0;
 }
 
-- 
2.1.4