[U-Boot] [PATCH 11/20] tegra: clock: Adjust PLL access to avoid a warning

[Simon Glass]

A harmless but confusing warning is displayed when looking up the
DisplayPort PLL. Correct this.

Signed-off-by: Simon Glass <sjg at chromium.org>
---

 arch/arm/cpu/tegra-common/clock.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/tegra-common/clock.c b/arch/arm/cpu/tegra-common/clock.c
index 5d53444..636be85 100644
--- a/arch/arm/cpu/tegra-common/clock.c
+++ b/arch/arm/cpu/tegra-common/clock.c
@@ -83,7 +83,7 @@ static struct clk_pll *get_pll(enum clock_id clkid)
 
 	assert(clock_id_is_pll(clkid));
 	if (clkid >= (enum clock_id)TEGRA_CLK_PLLS) {
-		debug("%s: Invalid PLL\n", __func__);
+		debug("%s: Invalid PLL %d\n", __func__, clkid);
 		return NULL;
 	}
 	return &clkrst->crc_pll[clkid];
@@ -119,9 +119,12 @@ int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
 unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
 		u32 divp, u32 cpcon, u32 lfcon)
 {
-	struct clk_pll *pll = get_pll(clkid);
+	struct clk_pll *pll = NULL;
 	u32 misc_data, data;
 
+	if (clkid < (enum clock_id)TEGRA_CLK_PLLS)
+		pll = get_pll(clkid);
+
 	/*
 	 * We cheat by treating all PLL (except PLLU) in the same fashion.
 	 * This works only because:
-- 
2.2.0.rc0.207.ga3a616c