[U-Boot] [PATCH 3/4] ARM / OMAP5: Add workaround for ARM errata 798870

[Nishanth Menon]

From: Praveen Rao <prao at ti.com>

This patch adds workaround for ARM errata 798870 which says
"If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache, the second
request (fill B) is then cancelled, and the second request would have
detected a hazard against a recent write or eviction (write B) to the
same cache line as fill B then the L2 logic might deadlock."

Note: Every SoC has slightly different manner of setting up access
to L2ACLR and similar registers since the Secure Monitor handling
of Secure Monitor Call(smc) is diverse. Hence an ARCH specific
macro is introduced to implement SoC specific errata workaround
implementations.

An intial implementation for OMAP5 and DRA7 is introduced here as well.
Obviously, implementations for other SoC families such as Exynos etc
will be widely different.

Signed-off-by: Praveen Rao <prao at ti.com>
Signed-off-by: Angela Stegmaier <angelabaker at ti.com>
Signed-off-by: Nishanth Menon <nm at ti.com>
---
 arch/arm/cpu/armv7/omap5/lowlevel_init.S |   35 ++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/omap5/lowlevel_init.S

diff --git a/arch/arm/cpu/armv7/omap5/lowlevel_init.S b/arch/arm/cpu/armv7/omap5/lowlevel_init.S
new file mode 100644
index 000000000000..1cc3c7af5fe2
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap5/lowlevel_init.S
@@ -0,0 +1,35 @@
+/*
+ * Board specific misc setup
+ *
+ * (C) Copyright 2015
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/arch/omap.h>
+#include <asm/omap_common.h>
+#include <asm/arch/spl.h>
+#include <linux/linkage.h>
+
+#ifdef CONFIG_ARM_ARCH_CP15_ERRATA
+	.globl	arch_cp15_errata_workaround
+ENTRY(arch_cp15_errata_workaround)
+	push	{r4-r11, lr}	@ save registers - ROM code may pollute
+
+#ifdef CONFIG_ARM_ERRATA_798870
+	mrc     p15, 0, r0, c0, c0, 0   @ Read Main ID Register (MIDR)
+	and     r0, r0, #0x000000f0     @ check rev
+	cmp     r0, #0x000000f0         @ compare rev
+	bne     skip_errata_798870      @ skip if not affected rev
+	mrc     p15, 1, r1, c15, c0, 0  @ read l2 aux ctrl reg
+	orr     r1, r1, #1 << 7         @ set bit #7
+	ldr     r0, =OMAP5_SERVICE_L2ACTLR_SET    @ Set L2 Cache Auxiliary control register - value in R0
+	b omap_smc1
+skip_errata_798870:
+#endif
+	pop	{r4-r11, pc}
+ENDPROC(arch_cp15_errata_workaround)
+
+#endif
-- 
1.7.9.5