[U-Boot] omap_gpmc: Do not default to HAM1 when SW ECC is selected

[Adam YH Lee]

The ECC scheme selection algorithm in OMAP GPMC appears to be left untested when
BCH8 handling code was added. Running 'nandecc sw' defaults to HAM1 even if
the board is using another scheme (ex. OMAP_ECC_BCH8_CODE_HW_DETECTION_SW on
OMAP3). This results in unrecoverable ECC errors when reading data. This commit
fixes the behavior by checking for CONFIG_BCH and using the scheme defined by
CONFIG_NAND_OMAP_ECCSCHEME in the board configuration file.

This has been tested on Gumstix Overo (OMAP3).

Signed-off-by: Adam YH Lee <adam.yh.lee at gmail.com>
---
 drivers/mtd/nand/omap_gpmc.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c
index fc64f48..5daf932 100644
--- a/drivers/mtd/nand/omap_gpmc.c
+++ b/drivers/mtd/nand/omap_gpmc.c
@@ -901,8 +901,13 @@ int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
 			return -EINVAL;
 		}
 	} else {
+		#ifdef CONFIG_BCH
+		err = omap_select_ecc_scheme(nand, CONFIG_NAND_OMAP_ECCSCHEME,
+					mtd->writesize, mtd->oobsize);
+		#else
 		err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW,
 					mtd->writesize, mtd->oobsize);
+		#endif
 	}
 
 	/* Update NAND handling after ECC mode switch */
-- 
1.9.1