[U-Boot] [linux-sunxi] [UBOOT] Both Linux-Sunxi and Mainline Uboot have issues

[Hans de Goede]

Hi,

On 19-02-15 13:38, Siarhei Siamashka wrote:
> On Wed, 18 Feb 2015 22:29:07 -0800 (PST)
> TsvetanUsunov <tsvetanusunov at gmail.com> wrote:
>
>> Hi
>>
>> For A13-OLinuxino till now we conservatively used the Linux-Sunxi uboot,
>> but we recently got new lot of Samsung memories and we decided to tweak
>> some parameters for this DDR in Linux-Sunxi uboot and found problems.
>> As this uboot is with status not maintained anymore I will not discuss the
>> problems, as probably no one will spend time on it,

<snip>

>> The PLL5 and PLL6 values are changed and this cause problems, this is what
>> we found so far:

<snip>

>> 1. mainline u-boot
>> =================
>> 1.1 pll5
>> address 0x01c20020, value 0xb1049091 - P=1, N=16, K=2, M=2.
>>   The PLL5 output for DDR = (24MHz*N*K)/M. DDR=24*16*2/2 = 384MHz
>> The PLL5 output for other module = (24MHz*N*K)/P. DDR=24*16*2/1 = 768MHz  -
>> This high frequency cause LCDs connected to the board to flicker
>
> Yes, this was already known. And had been addressed a long time ago.
> Hans has a more detailed reply, so I'm not going to duplicate it.
>
>> 1.2 pll6
>> address 0x01c20028, value 0xA1009900 - N=25, K=1, M=1

This is not the value set by u-boot, u-boot sets this to
0xA1009911

>>   The PLL6 output is (24MHz*N*K)/M/2 = 24*25*1/1/2 = 300MHz

And this formula from the A13 user manual is wrong I've run several
tests and the formula from the A10/A20 user manual, as used by the
allwinner kernel sources, upstream u-boot and upstream kernel:

PLL6 = (24MHz*N*K)/2

Is the correct one. This means that what u-boot is doing:

PLL6 = 0xA1009911, MBUS = 0x81000001

Results in PLL6 = 600 MHz , MBUS = 600 / 2 = 300 MHz so upstream
u-boot actually gives you more MBUS bandwidth to work with, as
intended.

But then the linux-sunxi-3.4 kernel comes along and sets PLL6 to:
0xA1009900 which translates to 300 MHz (in both the wrong and
correct formula) and you end up with an MBUS of only 150 MHz.



>> 1.3 MBUS clock
>> address 0x01c2015c, value 0x81000001  - MBUS clock source is PLL6/2 = 300/2
>> = 150MHz - This is connected to PLL6 setup, at this 150 Mhz the board cant
>> play video smoothly and sometimes drop video packets when the video is
>> playing
>
> Right. Having a reasonably fast MBUS clock speed is very important for
> performance.
>
>>   2. sunxi u-boot
>> =================
>> 1.1 pll5
>> address 0x01c20020, value 0xb1049091 - P=2, N=17, K=2, M=2.
>>   The PLL5 output for DDR = (24MHz*N*K)/M. DDR=24*17*2/2 = 408MHz
>> The PLL5 output for other module = (24MHz*N*K)/P. DDR=24*16*2/2 = 408MHz  -
>> this frequency was OK, There is no problem with LCD flickering, why the
>> frequency increase was necessary?
>> 1.2 pll6
>> address 0x01c20028, value 0xA1009900 - N=25, K=1, M=1
>>   The PLL6 output is (24MHz*N*K)/M/2 = 24*25*1/1/2 = 300MHz
>
> Thanks a lot for finding and reporting this particular problem.
>
> Based on a quick look, the most likely culprit seems to be the
> 'c' function in u-boot, which is providing wrong
> information to the DRAM code. But Hans is already working on a
> fix, so I'm not going to get involved yet.

Nope, the user manual for A13 is wrong (see above).

> Additionally, the sunxi-3.4 kernel is trying to re-configure PLL6 in
> 'arch/arm/mach-sun5i/clock/clock.c', which is a bit of a mess. As you
> have the problem, most likely it also ends up being 300MHz there.
> Probably the sunxi-3.4 kernel should not touch PLL6 at all and keep
> the settings from u-boot.

Oh, thanks for pointing that out, that explains why Tsvetan is seeing
0xA1009900 for the PLL6 setting, and explains his problem (see analysis
above).

I've attached a patch which should fix this, Tsvetan note that you
need to build with old kernel compatibility enabled for this fix to
work, as explained in my previous mail. Please let me know if this
fixes things then I'll push it upstream ASAP.

And someone should also write a kernel patch for the linux-sunxi kernel
to not touch pll6 on sun5i.

Regards,

Hans
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