[U-Boot] [PATCH v4 08/10] Exynos542x: Fix secondary core booting for thumb

[Akshay Saraswat]

When compiled SPL for Thumb secondary cores failed to boot
at the kernel boot up. Only one core came up out of 4.
This was happening because the code relocated to the
address 0x02073000 by the primary core was an ARM asm
code which was executed by the secondary cores as if it
was a thumb code.
This patch fixes the issue of secondary cores considering
relocated code as Thumb instructions and not ARM instructions
by jumping to the relocated with the help of "bx" ARM instruction.
"bx" instruction changes the 5th bit of CPSR which allows
execution unit to consider the following instructions as ARM
instructions.

Signed-off-by: Akshay Saraswat <akshay.s at samsung.com>
Reviewed-by: Simon Glass <sjg at chromium.org>
Tested-by: Simon Glass <sjg at chromium.org>
---
Changes since v3:
	- No change.

Changes since v2:
	- No change.

Changes since v1:
	- Added Reviewed-by & Tested-by.

 arch/arm/cpu/armv7/exynos/lowlevel_init.c | 2 +-
 arch/arm/include/asm/arch-exynos/system.h | 3 +++
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
index 0504576..782ecd1 100644
--- a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
+++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
@@ -89,7 +89,7 @@ static void secondary_cpu_start(void)
 {
 	v7_enable_smp(EXYNOS5420_INFORM_BASE);
 	svc32_mode_en();
-	set_pc(CONFIG_EXYNOS_RELOCATE_CODE_BASE);
+	branch_bx(CONFIG_EXYNOS_RELOCATE_CODE_BASE);
 }
 
 /*
diff --git a/arch/arm/include/asm/arch-exynos/system.h b/arch/arm/include/asm/arch-exynos/system.h
index 86903c3..a9fd5e6 100644
--- a/arch/arm/include/asm/arch-exynos/system.h
+++ b/arch/arm/include/asm/arch-exynos/system.h
@@ -75,6 +75,9 @@ struct exynos5_sysreg {
 /* Set program counter with the given value */
 #define set_pc(x) __asm__ __volatile__ ("mov     pc, %0\n\t" : : "r"(x))
 
+/* Branch to the given location */
+#define branch_bx(x) __asm__ __volatile__ ("bx	%0\n\t" : : "r"(x))
+
 /* Read Main Id register */
 #define mrc_midr(x) __asm__ __volatile__	\
 			("mrc     p15, 0, %0, c0, c0, 0\n\t" : "=r"(x) : )
-- 
1.9.1