[U-Boot] [u-boot PATCH v2 38/40] board: ti: AM43xx: added USB initializtion code
Kishon Vijay Abraham I
kishon at ti.com
Mon Feb 23 14:10:21 CET 2015
Implemented board_usb_init(), board_usb_cleanup() and
usb_gadget_handle_interrupts() in am43xx board file that
can be invoked by various gadget drivers.
Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>
Reviewed-by: Lukasz Majewski <l.majewski at samsung.com>
---
arch/arm/include/asm/arch-am33xx/hardware_am43xx.h | 9 ++
board/ti/am43xx/board.c | 108 ++++++++++++++++++++
2 files changed, 117 insertions(+)
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
index a8641aa..6a5773e 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
@@ -61,6 +61,15 @@
/* RTC base address */
#define RTC_BASE 0x44E3E000
+/* USB OTG */
+#define USB_OTG_SS1_BASE 0x48390000
+#define USB_OTG_SS1_GLUE_BASE 0x48380000
+#define USB2_PHY1_POWER 0x44E10620
+
+#define USB_OTG_SS2_BASE 0x483D0000
+#define USB_OTG_SS2_GLUE_BASE 0x483C0000
+#define USB2_PHY2_POWER 0x44E10628
+
/* USB Clock Control */
#define PRM_PER_USB_OTG_SS0_CLKCTRL (CM_PER + 0x260)
#define PRM_PER_USB_OTG_SS1_CLKCTRL (CM_PER + 0x268)
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index a1c3c17..a8796b1 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -12,6 +12,7 @@
#include <i2c.h>
#include <asm/errno.h>
#include <spl.h>
+#include <usb.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mux.h>
@@ -23,6 +24,10 @@
#include <power/tps65218.h>
#include <miiphy.h>
#include <cpsw.h>
+#include <linux/usb/gadget.h>
+#include <dwc3-uboot.h>
+#include <dwc3-omap-uboot.h>
+#include <ti-usb-phy-uboot.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -686,6 +691,109 @@ int board_late_init(void)
}
#endif
+#ifdef CONFIG_USB_DWC3
+static struct dwc3_device usb_otg_ss1 = {
+ .maximum_speed = USB_SPEED_HIGH,
+ .base = USB_OTG_SS1_BASE,
+ .tx_fifo_resize = false,
+ .index = 0,
+};
+
+static struct dwc3_omap_device usb_otg_ss1_glue = {
+ .base = (void *)USB_OTG_SS1_GLUE_BASE,
+ .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
+ .vbus_id_status = OMAP_DWC3_VBUS_VALID,
+ .index = 0,
+};
+
+static struct ti_usb_phy_device usb_phy1_device = {
+ .usb2_phy_power = (void *)USB2_PHY1_POWER,
+ .index = 0,
+};
+
+static struct dwc3_device usb_otg_ss2 = {
+ .maximum_speed = USB_SPEED_HIGH,
+ .base = USB_OTG_SS2_BASE,
+ .tx_fifo_resize = false,
+ .index = 1,
+};
+
+static struct dwc3_omap_device usb_otg_ss2_glue = {
+ .base = (void *)USB_OTG_SS2_GLUE_BASE,
+ .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
+ .vbus_id_status = OMAP_DWC3_VBUS_VALID,
+ .index = 1,
+};
+
+static struct ti_usb_phy_device usb_phy2_device = {
+ .usb2_phy_power = (void *)USB2_PHY2_POWER,
+ .index = 1,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ switch (index) {
+ case 0:
+ if (init == USB_INIT_DEVICE) {
+ usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
+ usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
+ } else {
+ usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
+ usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
+ }
+
+ dwc3_omap_uboot_init(&usb_otg_ss1_glue);
+ ti_usb_phy_uboot_init(&usb_phy1_device);
+ dwc3_uboot_init(&usb_otg_ss1);
+ break;
+ case 1:
+ if (init == USB_INIT_DEVICE) {
+ usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
+ usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
+ } else {
+ usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
+ usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
+ }
+
+ ti_usb_phy_uboot_init(&usb_phy2_device);
+ dwc3_omap_uboot_init(&usb_otg_ss2_glue);
+ dwc3_uboot_init(&usb_otg_ss2);
+ break;
+ default:
+ printf("Invalid Controller Index\n");
+ }
+
+ return 0;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+ switch (index) {
+ case 0:
+ case 1:
+ ti_usb_phy_uboot_exit(index);
+ dwc3_uboot_exit(index);
+ dwc3_omap_uboot_exit(index);
+ break;
+ default:
+ printf("Invalid Controller Index\n");
+ }
+
+ return 0;
+}
+
+int usb_gadget_handle_interrupts(void)
+{
+ u32 status;
+
+ status = dwc3_omap_uboot_interrupt_status(0);
+ if (status)
+ dwc3_uboot_handle_interrupt(0);
+
+ return 0;
+}
+#endif
+
#ifdef CONFIG_DRIVER_TI_CPSW
static void cpsw_control(int enabled)
--
1.7.9.5
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