[U-Boot] [PATCH] spl_mem_init.c : Added support for mDDR in SPL for i.MX28

[Marco Cavallini]

Signed-off-by: Marco Cavallini <m.cavallini at koansoftware.com>
---
 arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c |   18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
index a744e5d..9e11288 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
@@ -315,9 +315,27 @@ static void mx28_mem_init(void)
 
 	debug("SPL: Initialising mx28 SDRAM Controller\n");
 
+#ifndef CONFIG_SYS_MXS_mDDR
 	/* Set DDR2 mode */
 	writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2,
 		&pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set);
+#else
+	/* Set mDDR mode */
+	writel(	PINCTRL_EMI_DS_CTRL_ADDRESS_MA_MASK |
+		PINCTRL_EMI_DS_CTRL_CONTROL_MA_MASK |
+		PINCTRL_EMI_DS_CTRL_DUALPAD_MA_MASK |
+		PINCTRL_EMI_DS_CTRL_SLICE3_MA_MASK |
+		PINCTRL_EMI_DS_CTRL_SLICE2_MA_MASK |
+		PINCTRL_EMI_DS_CTRL_SLICE1_MA_MASK |
+		PINCTRL_EMI_DS_CTRL_SLICE0_MA_MASK,
+		&pinctrl_regs->hw_pinctrl_emi_ds_ctrl);
+
+	/* Configure Pins 0-15 as EMI pins */
+	writel(0, &pinctrl_regs->hw_pinctrl_muxsel10);
+	writel(0, &pinctrl_regs->hw_pinctrl_muxsel11);
+	writel(0, &pinctrl_regs->hw_pinctrl_muxsel12);
+	writel(0, &pinctrl_regs->hw_pinctrl_muxsel13);
+#endif
 
 	/*
 	 * Configure the DRAM registers
-- 
1.7.9.5