[U-Boot] [PATCH 4/6] x86: Move common Chromebook config into a separate file

[Bin Meng]

On Wed, Feb 11, 2015 at 9:59 AM, Simon Glass <sjg at chromium.org> wrote:
> Since Chromebooks mostly have similar configuration, put it in a common
> file.
>
> Signed-off-by: Simon Glass <sjg at chromium.org>
> ---
>
>  include/configs/chromebook_link.h | 61 +----------------------------------
>  include/configs/x86-chromebook.h  | 68 +++++++++++++++++++++++++++++++++++++++
>  2 files changed, 69 insertions(+), 60 deletions(-)
>  create mode 100644 include/configs/x86-chromebook.h
>
> diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h
> index 7b460e8..5265787 100644
> --- a/include/configs/chromebook_link.h
> +++ b/include/configs/chromebook_link.h
> @@ -14,65 +14,6 @@
>  #define __CONFIG_H
>
>  #include <configs/x86-common.h>
> -
> -
> -#define CONFIG_SYS_MONITOR_LEN                 (1 << 20)
> -
> -#define CONFIG_DCACHE_RAM_MRC_VAR_SIZE         0x4000
> -#define CONFIG_BOARD_EARLY_INIT_F
> -#define CONFIG_MISC_INIT_R
> -
> -#define CONFIG_NR_DRAM_BANKS                   8
> -#define CONFIG_X86_MRC_ADDR                    0xfffa0000
> -#define CONFIG_CACHE_MRC_SIZE_KB               512
> -
> -#define CONFIG_X86_SERIAL
> -
> -#define CONFIG_SCSI_DEV_LIST           {PCI_VENDOR_ID_INTEL, \
> -                       PCI_DEVICE_ID_INTEL_NM10_AHCI},       \
> -       {PCI_VENDOR_ID_INTEL,           \
> -                       PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
> -       {PCI_VENDOR_ID_INTEL, \
> -                       PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
> -       {PCI_VENDOR_ID_INTEL,           \
> -                       PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
> -
> -#define CONFIG_X86_OPTION_ROM_FILE             pci8086,0166.bin
> -#define CONFIG_X86_OPTION_ROM_ADDR             0xfff90000
> -
> -#define CONFIG_PCI_MEM_BUS     0xe0000000
> -#define CONFIG_PCI_MEM_PHYS    CONFIG_PCI_MEM_BUS
> -#define CONFIG_PCI_MEM_SIZE    0x10000000
> -
> -#define CONFIG_PCI_PREF_BUS    0xd0000000
> -#define CONFIG_PCI_PREF_PHYS   CONFIG_PCI_PREF_BUS
> -#define CONFIG_PCI_PREF_SIZE   0x10000000
> -
> -#define CONFIG_PCI_IO_BUS      0x1000
> -#define CONFIG_PCI_IO_PHYS     CONFIG_PCI_IO_BUS
> -#define CONFIG_PCI_IO_SIZE     0xefff
> -
> -#define CONFIG_SYS_EARLY_PCI_INIT
> -#define CONFIG_PCI_PNP
> -
> -#define CONFIG_BIOSEMU
> -#define VIDEO_IO_OFFSET                                0
> -#define CONFIG_X86EMU_RAW_IO
> -
> -#define CONFIG_CROS_EC
> -#define CONFIG_CROS_EC_LPC
> -#define CONFIG_CMD_CROS_EC
> -#define CONFIG_ARCH_EARLY_INIT_R
> -
> -#undef CONFIG_ENV_IS_NOWHERE
> -#undef CONFIG_ENV_SIZE
> -#define CONFIG_ENV_SIZE                        0x1000
> -#define CONFIG_ENV_SECT_SIZE           0x1000
> -#define CONFIG_ENV_IS_IN_SPI_FLASH
> -#define CONFIG_ENV_OFFSET              0x003f8000
> -
> -#define CONFIG_STD_DEVICES_SETTINGS     "stdin=usbkbd,vga,serial\0" \
> -                                       "stdout=vga,serial\0" \
> -                                       "stderr=vga,serial\0"
> +#include <configs/x86-chromebook.h>
>
>  #endif /* __CONFIG_H */
> diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h
> new file mode 100644
> index 0000000..b6a76fe
> --- /dev/null
> +++ b/include/configs/x86-chromebook.h
> @@ -0,0 +1,68 @@
> +/*
> + *
> + * Copyright (c) 2015 Google, Inc
> + *
> + * SPDX-License-Identifier:    GPL-2.0+
> + */
> +
> +#ifndef _X86_CHROMEBOOK_H
> +#define _X86_CHROMEBOOK_H
> +
> +#define CONFIG_SYS_MONITOR_LEN                 (1 << 20)
> +
> +#define CONFIG_DCACHE_RAM_MRC_VAR_SIZE         0x4000
> +#define CONFIG_BOARD_EARLY_INIT_F
> +#define CONFIG_MISC_INIT_R
> +
> +#define CONFIG_NR_DRAM_BANKS                   8
> +#define CONFIG_X86_MRC_ADDR                    0xfffa0000
> +#define CONFIG_CACHE_MRC_SIZE_KB               512
> +
> +#define CONFIG_X86_SERIAL
> +
> +#define CONFIG_SCSI_DEV_LIST   \
> +       {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM10_AHCI}, \
> +       {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
> +       {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
> +       {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}, \
> +       {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_AHCI}
> +
> +#define CONFIG_X86_OPTION_ROM_FILE             pci8086,0166.bin
> +#define CONFIG_X86_OPTION_ROM_ADDR             0xfff90000
> +
> +#define CONFIG_PCI_MEM_BUS     0xe0000000
> +#define CONFIG_PCI_MEM_PHYS    CONFIG_PCI_MEM_BUS
> +#define CONFIG_PCI_MEM_SIZE    0x10000000
> +
> +#define CONFIG_PCI_PREF_BUS    0xd0000000
> +#define CONFIG_PCI_PREF_PHYS   CONFIG_PCI_PREF_BUS
> +#define CONFIG_PCI_PREF_SIZE   0x10000000
> +
> +#define CONFIG_PCI_IO_BUS      0x1000
> +#define CONFIG_PCI_IO_PHYS     CONFIG_PCI_IO_BUS
> +#define CONFIG_PCI_IO_SIZE     0xefff
> +
> +#define CONFIG_SYS_EARLY_PCI_INIT
> +#define CONFIG_PCI_PNP
> +
> +#define CONFIG_BIOSEMU
> +#define VIDEO_IO_OFFSET                                0
> +#define CONFIG_X86EMU_RAW_IO
> +
> +#define CONFIG_CROS_EC
> +#define CONFIG_CROS_EC_LPC
> +#define CONFIG_CMD_CROS_EC
> +#define CONFIG_ARCH_EARLY_INIT_R
> +
> +#undef CONFIG_ENV_IS_NOWHERE
> +#undef CONFIG_ENV_SIZE
> +#define CONFIG_ENV_SIZE                        0x1000
> +#define CONFIG_ENV_SECT_SIZE           0x1000
> +#define CONFIG_ENV_IS_IN_SPI_FLASH
> +#define CONFIG_ENV_OFFSET              0x003f8000
> +
> +#define CONFIG_STD_DEVICES_SETTINGS     "stdin=usbkbd,vga,serial\0" \
> +                                       "stdout=vga,serial\0" \
> +                                       "stderr=vga,serial\0"
> +
> +#endif
> --

Reviewed-by: Bin Meng <bmeng.cn at gmail.com>