[U-Boot] [PATCH 25/29] rockchip: Add base SoC files

Simon Glass sjg at chromium.org
Sat Feb 28 06:06:49 CET 2015


Add some basic files required to allow the SoC to start up. This is a
minimal set, enough only to display a serial message in SPL and hang.

Signed-off-by: Simon Glass <sjg at chromium.org>
---

 arch/arm/Kconfig                           |   9 ++
 arch/arm/Makefile                          |   1 +
 arch/arm/include/asm/arch-rockchip/clock.h |  12 ++
 arch/arm/include/asm/arch-rockchip/gpio.h  |   5 +
 arch/arm/include/asm/arch-rockchip/grf.h   | 181 +++++++++++++++++++++++++++++
 arch/arm/mach-rockchip/Kconfig             |  44 +++++++
 arch/arm/mach-rockchip/Makefile            |  12 ++
 arch/arm/mach-rockchip/board-spl.c         |  54 +++++++++
 arch/arm/mach-rockchip/board.c             |  17 +++
 arch/arm/mach-rockchip/common.c            |  11 ++
 arch/arm/mach-rockchip/rk3288/Kconfig      |   6 +
 11 files changed, 352 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-rockchip/clock.h
 create mode 100644 arch/arm/include/asm/arch-rockchip/gpio.h
 create mode 100644 arch/arm/include/asm/arch-rockchip/grf.h
 create mode 100644 arch/arm/mach-rockchip/Kconfig
 create mode 100644 arch/arm/mach-rockchip/Makefile
 create mode 100644 arch/arm/mach-rockchip/board-spl.c
 create mode 100644 arch/arm/mach-rockchip/board.c
 create mode 100644 arch/arm/mach-rockchip/common.c
 create mode 100644 arch/arm/mach-rockchip/rk3288/Kconfig

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f0e6dec..1eee2d8 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -693,6 +693,13 @@ config ARCH_UNIPHIER
 	select OF_CONTROL
 	select SPL_DISABLE_OF_CONTROL
 
+config ARCH_ROCKCHIP
+	bool "Support Rockchip SoCs"
+	select SUPPORT_SPL
+	select SPL
+	select OF_CONTROL
+	select CPU_V7
+
 endchoice
 
 source "arch/arm/mach-at91/Kconfig"
@@ -721,6 +728,8 @@ source "arch/arm/mach-orion5x/Kconfig"
 
 source "arch/arm/cpu/armv7/rmobile/Kconfig"
 
+source "arch/arm/mach-rockchip/Kconfig"
+
 source "arch/arm/cpu/armv7/s5pc1xx/Kconfig"
 
 source "arch/arm/mach-tegra/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 878ae26..29945c4 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -14,6 +14,7 @@ machine-$(CONFIG_KIRKWOOD)		+= kirkwood
 machine-$(CONFIG_ARCH_NOMADIK)		+= nomadik
 # TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
 machine-$(CONFIG_ORION5X)		+= orion5x
+machine-$(CONFIG_ARCH_ROCKCHIP)		+= rockchip
 machine-$(CONFIG_TEGRA)			+= tegra
 machine-$(CONFIG_ARCH_VERSATILE)	+= versatile
 
diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h
new file mode 100644
index 0000000..9314585
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/clock.h
@@ -0,0 +1,12 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _ASM_ARCH_CLOCK_H
+#define _ASM_ARCH_CLOCK_H
+
+#define OSC_HZ		(24 * 1000 * 1000)
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/gpio.h b/arch/arm/include/asm/arch-rockchip/gpio.h
new file mode 100644
index 0000000..607949c
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/gpio.h
@@ -0,0 +1,5 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
diff --git a/arch/arm/include/asm/arch-rockchip/grf.h b/arch/arm/include/asm/arch-rockchip/grf.h
new file mode 100644
index 0000000..8722a89
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf.h
@@ -0,0 +1,181 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ * Copyright 2014 Rockchip Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ *
+ * From coreboot file of the same name
+ */
+
+#ifndef _ASM_ARCH_GRF_H
+#define _ASM_ARCH_GRF_H
+
+struct rk3288_grf_gpio_lh {
+	u32 l;
+	u32 h;
+};
+
+struct rk3288_grf_regs {
+	u32 reserved[3];
+	union {
+		u32 gpio1d_iomux;
+		u32 iomux_lcdc;
+	};
+	u32 gpio2a_iomux;
+	u32 gpio2b_iomux;
+	union {
+		u32 gpio2c_iomux;
+		u32 iomux_i2c3;
+	};
+	u32 reserved2;
+	union {
+		u32 gpio3a_iomux;
+		u32 iomux_emmcdata;
+	};
+	union {
+		u32 gpio3b_iomux;
+		u32 iomux_emmcpwren;
+	};
+	union {
+		u32 gpio3c_iomux;
+		u32 iomux_emmccmd;
+	};
+	u32 gpio3dl_iomux;
+	u32 gpio3dh_iomux;
+	u32 gpio4al_iomux;
+	u32 gpio4ah_iomux;
+	u32 gpio4bl_iomux;
+	u32 reserved3;
+	u32 gpio4c_iomux;
+	u32 gpio4d_iomux;
+	u32 reserved4;
+	union {
+		u32 gpio5b_iomux;
+		u32 iomux_spi0;
+	};
+	u32 gpio5c_iomux;
+	u32 reserved5;
+	union {
+		u32 gpio6a_iomux;
+		u32 iomux_i2s;
+	};
+	union {
+		u32 gpio6b_iomux;
+		u32 iomux_i2c2;
+		u32 iomux_i2sclk;
+	};
+	union {
+		u32 gpio6c_iomux;
+		u32 iomux_sdmmc0;
+	};
+	u32 reserved6;
+	union {
+		u32 gpio7a_iomux;
+		u32 iomux_pwm0;
+		u32 iomux_pwm1;
+	};
+	union {
+		u32 gpio7b_iomux;
+		u32 iomux_edp_hotplug;
+	};
+	union {
+		u32 gpio7cl_iomux;
+		u32 iomux_i2c5sda;
+		u32 iomux_i2c4;
+	};
+	union {
+		u32 gpio7ch_iomux;
+		u32 iomux_uart2;
+		u32 iomux_i2c5scl;
+	};
+	u32 reserved7;
+	union {
+		u32 gpio8a_iomux;
+		u32 iomux_spi2csclk;
+		u32 iomux_i2c1;
+	};
+	union {
+		u32 gpio8b_iomux;
+		u32 iomux_spi2txrx;
+	};
+	u32 reserved8[30];
+	struct rk3288_grf_gpio_lh gpio_sr[8];
+	u32 gpio1_p[8][4];
+	u32 gpio1_e[8][4];
+	u32 gpio_smt;
+	u32 soc_con0;
+	u32 soc_con1;
+	u32 soc_con2;
+	u32 soc_con3;
+	u32 soc_con4;
+	u32 soc_con5;
+	u32 soc_con6;
+	u32 soc_con7;
+	u32 soc_con8;
+	u32 soc_con9;
+	u32 soc_con10;
+	u32 soc_con11;
+	u32 soc_con12;
+	u32 soc_con13;
+	u32 soc_con14;
+	u32 soc_status[22];
+	u32 reserved9[2];
+	u32 peridmac_con[4];
+	u32 ddrc0_con0;
+	u32 ddrc1_con0;
+	u32 cpu_con[5];
+	u32 reserved10[3];
+	u32 cpu_status0;
+	u32 reserved11;
+	u32 uoc0_con[5];
+	u32 uoc1_con[5];
+	u32 uoc2_con[4];
+	u32 uoc3_con[2];
+	u32 uoc4_con[2];
+	u32 pvtm_con[3];
+	u32 pvtm_status[3];
+	u32 io_vsel;
+	u32 saradc_testbit;
+	u32 tsadc_testbit_l;
+	u32 tsadc_testbit_h;
+	u32 os_reg[4];
+	u32 reserved12;
+	u32 soc_con15;
+	u32 soc_con16;
+};
+
+struct rk3288_sgrf_regs {
+	u32 soc_con0;
+	u32 soc_con1;
+	u32 soc_con2;
+	u32 soc_con3;
+	u32 soc_con4;
+	u32 soc_con5;
+	u32 reserved1[(0x20-0x18)/4];
+	u32 busdmac_con[2];
+	u32 reserved2[(0x40-0x28)/4];
+	u32 cpu_con[3];
+	u32 reserved3[(0x50-0x4c)/4];
+	u32 soc_con6;
+	u32 soc_con7;
+	u32 soc_con8;
+	u32 soc_con9;
+	u32 soc_con10;
+	u32 soc_con11;
+	u32 soc_con12;
+	u32 soc_con13;
+	u32 soc_con14;
+	u32 soc_con15;
+	u32 soc_con16;
+	u32 soc_con17;
+	u32 soc_con18;
+	u32 soc_con19;
+	u32 soc_con20;
+	u32 soc_con21;
+	u32 reserved4[(0x100-0x90)/4];
+	u32 soc_status[2];
+	u32 reserved5[(0x120-0x108)/4];
+	u32 fast_boot_addr;
+};
+
+#endif
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
new file mode 100644
index 0000000..dba0a45
--- /dev/null
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -0,0 +1,44 @@
+if ARCH_ROCKCHIP
+
+config ROCKCHIP_RK3288
+	bool "Support Rockchip RK3288"
+	help
+	  The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
+	  including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
+	  video interfaces supporting HDMI and eDP, several DDR3 options
+	  and video codec support. Peripherals include Gigabit Ethernet,
+	  USB2 host and OTG, SDIO, I2S, UART,s, SPI, I2C and PWMs.
+
+config SYS_MALLOC_F
+	default y
+
+config SYS_MALLOC_F_LEN
+	default 0x800
+
+config DM
+	default y
+
+config SPL_DM
+	default y
+
+config DM_SERIAL
+	default y
+
+config DM_SPI
+	default y
+
+config DM_SPI_FLASH
+	default y
+
+config DM_I2C
+	default y
+
+config DM_GPIO
+	default y
+
+config ROCKCHIP_SERIAL
+	default y
+
+source "arch/arm/mach-rockchip/rk3288/Kconfig"
+
+endif
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
new file mode 100644
index 0000000..0cef0a2
--- /dev/null
+++ b/arch/arm/mach-rockchip/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright (c) 2014 Google, Inc
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y += board-spl.o
+else
+obj-y += board.o
+endif
+obj-y += common.o
diff --git a/arch/arm/mach-rockchip/board-spl.c b/arch/arm/mach-rockchip/board-spl.c
new file mode 100644
index 0000000..a6e0ec9
--- /dev/null
+++ b/arch/arm/mach-rockchip/board-spl.c
@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <malloc.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/grf.h>
+#include <dm/root.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define RK_CLRSETBITS(clr, set) ((((clr) | (set)) << 16) | set)
+#define IOMUX_UART2	RK_CLRSETBITS(7 << 12 | 3 << 8, 1 << 12 | 1 << 8)
+#define GRF_BASE		0xFF770000
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_SPI;
+}
+
+void spl_board_load_image(void)
+{
+}
+
+void board_init_f(ulong dummy)
+{
+	struct rk3288_grf_regs * const rk3288_grf = (void *)GRF_BASE;
+
+	writel(IOMUX_UART2, &rk3288_grf->iomux_uart2);
+
+	/*
+	 * Debug UART can be used from here if required:
+	 *
+	 * debug_uart_init();
+	 * printch('a');
+	 * printhex8(0x1234);
+	 * printascii("string");
+	 */
+
+	/* Clear the BSS */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	board_init_r(NULL, 0);
+}
+
+void spl_board_init(void)
+{
+	preloader_console_init();
+}
diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
new file mode 100644
index 0000000..38d2b40
--- /dev/null
+++ b/arch/arm/mach-rockchip/board.c
@@ -0,0 +1,17 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+	return 0;
+}
diff --git a/arch/arm/mach-rockchip/common.c b/arch/arm/mach-rockchip/common.c
new file mode 100644
index 0000000..51ea34d
--- /dev/null
+++ b/arch/arm/mach-rockchip/common.c
@@ -0,0 +1,11 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+
+void reset_cpu(ulong addr)
+{
+}
diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig
new file mode 100644
index 0000000..26d5951
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3288/Kconfig
@@ -0,0 +1,6 @@
+if ROCKCHIP_RK3288
+
+config SYS_SOC
+	default "rockchip"
+
+endif
-- 
2.2.0.rc0.207.ga3a616c



More information about the U-Boot mailing list