[U-Boot] [PATCH] spi: designware_spi: Fix detecting FIFO depth

[Jagan Teki]

On 6 January 2015 at 15:28, Stefan Roese <sr at denx.de> wrote:
> On 06.01.2015 01:08, Axel Lin wrote:
>>
>> Current code tries to find the highest valid fifo depth by checking the
>> value
>> it wrote to DW_SPI_TXFLTR. There are a few problems in current code:
>> 1) There is an off-by-one in dws->fifo_len setting because it assumes the
>> latest
>>     register write fails so the latest valid value should be fifo - 1.
>> 2) We know the depth could be from 2 to 256 from HW spec, so it is not
>> necessary
>>     to test fifo == 257. In the case fifo is 257, it means the latest
>> valid
>>     setting is fifo = 256. So after the for loop iteration, we should
>> check
>>     fifo == 2 case instead of fifo == 257 if detecting the FIFO depth
>> fails.
>> This patch fixes above issues.
>>
>> Signed-off-by: Axel Lin <axel.lin at ingics.com>
>
>
> Acked-by: Stefan Roese <sr at denx.de>

Applied to u-boot-spi/master

thanks!
-- 
Jagan.