[U-Boot] Odroid XU3 - exynos5422 - SPL - iRAM/sRAM address

[Suriyan Ramasami]

Hello Sjoerd Simons,
   A signed BL2 which allows unsigned BL2 chain load is already
available for experimentation. Refer this link:
http://forum.odroid.com/viewtopic.php?f=98&t=6147#p58984
The suriyan.bl2-hkxu3.1212.5422.zip blob contains a signed BL2 which
allows the same.
The layout of SD card is as follows:

BL1 (1 to 30) 15K
BL2 (31 to 62) 16K
indicator block (63 to 64) 1K
uboot (65 to 2112) 1M
tzsw (2113 to 2624) 256K
unsigned BL2 (2625 to 2656) 16K

A non zero in the first byte of the indicator block instructs the
signed BL2 to load the unsigned BL2 @ offset 2625.

Thanks
- Suriyan


On Tue, Jan 20, 2015 at 8:40 AM, Sjoerd Simons
<sjoerd.simons at collabora.co.uk> wrote:
> (Corrected the u-boot list address in the cc of this thread and added
>  Kevin hilman who is also quite interested in this topic)
>
> On Tue, 2015-01-20 at 10:36 +0100, Sjoerd Simons wrote:
>> Hey Suriyan,
>>
>> I just noticed the patchset Akshay Saraswat sent (Add support for
>> booting multiple cores), which would hopefully fix  some issues wrt.
>> booting secondary cores we've seen on the XU3 thusfar. Unfortunately,
>> those fixes need to be applied in the SPL stage, hence coming back to
>> the BL2 story :). Any updates you can share?
>>
>> Separately i do wonder if getting a (very basic?) signed BL2 to
>> chainload an unsigned SPL might not be the best way forward here. Would
>> allow us to fix SPL issues in u-boot without having to ask hardkernel to
>> sign every time ? :/
>>
>>
>> On Fri, 2014-12-19 at 15:45 -0800, Suriyan Ramasami wrote:
>> > Just to close the loop.
>> >
>> > For the XU3, scanning memory, I found the signed BL2 loaded at address
>> > 0x02027000.
>> > Regards
>> > - Suriyan
>> >
>> > PS: Any pointers with regards to mem_ctrl_init() is appreciated.
>> >
>> > On Fri, Dec 19, 2014 at 12:43 PM, Suriyan Ramasami <suriyan.r at gmail.com> wrote:
>> > > Hello All,
>> > >     Greetings!
>> > >
>> > >     I have been dabbling with trying to get mainline SPL working on
>> > > the Odroid XU3. The issue that I am facing is that currently I do not
>> > > know what address the BL1 loads and passes control to the SPL (signed
>> > > BL2).
>> > >     Of course, I could get another SPL signed from Hard kernel and
>> > > have the address written out in some memory address, but I thought if
>> > > someone has access to the documents it might be faster to get this
>> > > information.
>> > >
>> > > As an update ...
>> > >     So far, I have successfully gotten an Hardkernel based SPL to
>> > > chain load an unsigned SPL from mainline. I am hitting some issues in
>> > > mem_ctrl_init() or so I think. I was wondering if the issues were
>> > > cause of it being initialized twice (one from the signed BL2) and the
>> > > other from the mainline SPL that is chain loaded.
>> > >
>> > > Thanks
>> > > - Suriyan
>>
>>
>
>