[U-Boot] [PATCH 0/23] x86: Add bare support for Intel Minnowboard Max
Simon Glass
sjg at chromium.org
Tue Jan 27 02:22:58 CET 2015
This series adds support for the Intel Minnowboard Max (called Minnowmax
for short). Along the way a few refactors and additions are made:
- The Intel Firmware Support Package support is moved from queensbay to a
common location
- PCI support for XHCI is added
- A few tweaks are made to the PCI support
- Support for the debug UART (early debug output) is provided
- The microcode tool now also supports reading in header files
This board has been lightly tested. The following seem to work:
- USB2 on the blue port (not USB3), e.g. for keyboard
- Ethernet
- HDMI out and console
- UART
- uSD card
- SPI
SATA is detected but I have not attached a drive to try it. USB3 shows signs
of life but does not detect a USB stick, and crashes when trying to use a
USB Ethernet adaptor.
For SPI some parts cannot be read and others cannot be written. This seems
to be a feature of the Intel hardware configuration. It may be possible to
fix this using the SPI registers but I cannot work out how / lost interest
trying. So far, addresses from 500000 to 700000 can be used.
I have not tried the ICH GPIO driver but it likely needs work before it will
function. I2C is not supported as there is currently no U-Boot driver for
this.
The zboot command can be used to start a bzImage kernel. Verified boot is
supported - use mkimage to sign images as described in this walk-through:
doc/uImage.FIT/beaglebone_vboot.txt
Boot time is grim:
- 1423ms to set up display (Intel FSP)
- 454ms to scan AHCI (when no devices are connected)
- ~1000ms to power up and start cache-as-RAM init (Intel FSP)
(this is not benchmarked, may be inaccurate)
- ~950ms to set up memory and initial machine configuration (Intel FSP)
(this is not benchmarked, may be inaccurate)
So it takes over 4 seconds to get to booting a kernel.
Implementing the Memory Reference Code (MRC) cache should improve this
slightly (perhaps a reduction of 500-1000ms). This cache is implemented for
ivybridge so that code needs to be moved into a generic x86 directory and
plumbed into the FSP code. This has not been done in this series. Also the
video and SATA/AHCI can be disabled if preferred.
It is also possible to run as a coreboot payload. See the instructions in
README.x86 for this. In this case video does not work since coreboot does
not pass through the VESA display information.
To support the single-core 1GB variant, changes would need to be made to
arch/x86/cpu/baytrail/fsp_configs.c to select different values for the
memory. The microcode update may need to change also.
This series is available at u-boot-x86 branch minnow-working.
Simon Glass (23):
x86: Enhance the microcode tool to support header files as input
pci: Add a function to find a device by class
x86: pci: Add PCI IDs for Minnowboard Max
x86: video: Enable video for Minnowboard Max
usb: pci: Use pci_find_class() to find the device
usb: pci: Add XHCI driver for PCI
x86: Add an option to enabling building a ROM file
x86: Make MMCONF_BASE_ADDRESS common across x86
x86: video: Allow video ROM execution to fall back to the other method
x86: bootstage: Add time measurement for vesa start-up
x86: Move common FSP code into a common location
x86: Adjust the FSP types slightly
x86: Make CAR and DRAM FSP code common
x86: Move common FSP functions into a common file
x86: Remove unnecessary casts and fix comment typos
x86: Allow FSP Kconfig settings for all x86
x86: Define cache line size
x86: Allow a UART to be set up before the FSP is ready
x86: spi: Support ValleyView in ICH SPI driver
scsi: bootstage: Measure time taken to scan the bus
x86: Enable bootstage features
x86: Add some documentation on how to port U-Boot on x86
x86: Add support for Intel Minnowboard Max
Makefile | 5 +-
arch/x86/Kconfig | 62 +
arch/x86/cpu/Makefile | 1 +
arch/x86/cpu/baytrail/Kconfig | 9 +
arch/x86/cpu/baytrail/Makefile | 10 +
arch/x86/cpu/baytrail/early_uart.c | 82 +
arch/x86/cpu/baytrail/fsp_configs.c | 156 +
arch/x86/cpu/baytrail/pci.c | 47 +
arch/x86/cpu/baytrail/valleyview.c | 37 +
arch/x86/cpu/ivybridge/gma.c | 3 +-
arch/x86/cpu/queensbay/Kconfig | 38 -
arch/x86/cpu/queensbay/Makefile | 4 +-
arch/x86/cpu/queensbay/fsp_configs.c | 2 +-
arch/x86/cpu/queensbay/tnc.c | 29 +-
arch/x86/cpu/queensbay/tnc_pci.c | 17 +-
arch/x86/cpu/queensbay/topcliff.c | 32 +-
arch/x86/dts/Makefile | 3 +-
arch/x86/dts/microcode/m0130673322.dtsi | 3284 ++++++++++++++++++++
arch/x86/dts/minnowmax.dts | 45 +
arch/x86/dts/serial.dtsi | 2 +-
arch/x86/include/asm/arch-baytrail/fsp/azalia.h | 39 +
arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h | 95 +
arch/x86/include/asm/arch-baytrail/gpio.h | 13 +
arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h | 2 -
arch/x86/include/asm/cache.h | 2 +
.../include/asm/{arch-queensbay => }/fsp/fsp_api.h | 6 +-
.../asm/{arch-queensbay => }/fsp/fsp_bootmode.h | 0
.../include/asm/{arch-queensbay => }/fsp/fsp_ffs.h | 0
.../include/asm/{arch-queensbay => }/fsp/fsp_fv.h | 0
.../include/asm/{arch-queensbay => }/fsp/fsp_hob.h | 0
.../asm/{arch-queensbay => }/fsp/fsp_infoheader.h | 0
.../asm/{arch-queensbay => }/fsp/fsp_platform.h | 0
.../asm/{arch-queensbay => }/fsp/fsp_support.h | 6 +-
.../asm/{arch-queensbay => }/fsp/fsp_types.h | 0
arch/x86/include/asm/u-boot-x86.h | 20 +
arch/x86/lib/Makefile | 1 +
arch/x86/lib/cmd_hob.c | 2 +-
arch/x86/lib/fsp/Makefile | 10 +
.../{cpu/queensbay/tnc_car.S => lib/fsp/fsp_car.S} | 0
arch/x86/lib/fsp/fsp_common.c | 88 +
.../queensbay/tnc_dram.c => lib/fsp/fsp_dram.c} | 2 +-
arch/x86/{cpu/queensbay => lib/fsp}/fsp_support.c | 20 +-
board/google/chromebook_link/Kconfig | 1 -
board/intel/minnowmax/Kconfig | 31 +
board/intel/minnowmax/MAINTAINERS | 6 +
board/intel/minnowmax/Makefile | 7 +
board/intel/minnowmax/minnowmax.c | 32 +
board/intel/minnowmax/start.S | 9 +
common/cmd_scsi.c | 2 +
configs/minnowmax_defconfig | 13 +
doc/README.x86 | 120 +-
drivers/pci/pci.c | 38 +
drivers/pci/pci_rom.c | 32 +-
drivers/spi/ich.c | 56 +-
drivers/spi/ich.h | 11 +-
drivers/usb/host/Makefile | 1 +
drivers/usb/host/ehci-pci.c | 53 +-
drivers/usb/host/xhci-pci.c | 60 +
drivers/video/vesa_fb.c | 9 +-
include/bootstage.h | 1 +
include/configs/minnowmax.h | 69 +
include/configs/x86-common.h | 3 +
include/pci.h | 3 +-
include/pci_ids.h | 5 +
include/pci_rom.h | 15 +-
tools/microcode-tool.py | 90 +-
66 files changed, 4589 insertions(+), 252 deletions(-)
create mode 100644 arch/x86/cpu/baytrail/Kconfig
create mode 100644 arch/x86/cpu/baytrail/Makefile
create mode 100644 arch/x86/cpu/baytrail/early_uart.c
create mode 100644 arch/x86/cpu/baytrail/fsp_configs.c
create mode 100644 arch/x86/cpu/baytrail/pci.c
create mode 100644 arch/x86/cpu/baytrail/valleyview.c
create mode 100644 arch/x86/dts/microcode/m0130673322.dtsi
create mode 100644 arch/x86/dts/minnowmax.dts
create mode 100644 arch/x86/include/asm/arch-baytrail/fsp/azalia.h
create mode 100644 arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h
create mode 100644 arch/x86/include/asm/arch-baytrail/gpio.h
rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_api.h (88%)
rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_bootmode.h (100%)
rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_ffs.h (100%)
rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_fv.h (100%)
rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_hob.h (100%)
rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_infoheader.h (100%)
rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_platform.h (100%)
rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_support.h (98%)
rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_types.h (100%)
create mode 100644 arch/x86/lib/fsp/Makefile
rename arch/x86/{cpu/queensbay/tnc_car.S => lib/fsp/fsp_car.S} (100%)
create mode 100644 arch/x86/lib/fsp/fsp_common.c
rename arch/x86/{cpu/queensbay/tnc_dram.c => lib/fsp/fsp_dram.c} (98%)
rename arch/x86/{cpu/queensbay => lib/fsp}/fsp_support.c (96%)
create mode 100644 board/intel/minnowmax/Kconfig
create mode 100644 board/intel/minnowmax/MAINTAINERS
create mode 100644 board/intel/minnowmax/Makefile
create mode 100644 board/intel/minnowmax/minnowmax.c
create mode 100644 board/intel/minnowmax/start.S
create mode 100644 configs/minnowmax_defconfig
create mode 100644 drivers/usb/host/xhci-pci.c
create mode 100644 include/configs/minnowmax.h
--
2.2.0.rc0.207.ga3a616c
More information about the U-Boot
mailing list