[U-Boot] [PATCH v3 03/25] rockchip: rk3288: dts: Make core devices available early

Simon Glass sjg at chromium.org
Wed Jun 24 01:28:48 CEST 2015


In SPL we need access to the CRU and other peripherals so we can set up
SDRAM. Mark these so that they will remain in the device tree.

Signed-off-by: Simon Glass <sjg at chromium.org>
---

Changes in v3: None
Changes in v2: None

 arch/arm/dts/rk3288.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
index 6b5145c..0f49709 100644
--- a/arch/arm/dts/rk3288.dtsi
+++ b/arch/arm/dts/rk3288.dtsi
@@ -16,6 +16,15 @@
 
 	interrupt-parent = <&gic>;
 	aliases {
+		gpio0 = &gpio0;
+		gpio1 = &gpio1;
+		gpio2 = &gpio2;
+		gpio3 = &gpio3;
+		gpio4 = &gpio4;
+		gpio5 = &gpio5;
+		gpio6 = &gpio6;
+		gpio7 = &gpio7;
+		gpio8 = &gpio8;
 		i2c0 = &i2c0;
 		i2c1 = &i2c1;
 		i2c2 = &i2c2;
@@ -454,6 +463,7 @@
 	};
 
 	dmc: dmc at ff610000 {
+		u-boot,dm-pre-reloc;
 		compatible = "rockchip,rk3288-dmc", "syscon";
 		rockchip,cru = <&cru>;
 		rockchip,grf = <&grf>;
@@ -569,11 +579,13 @@
 	};
 
 	pmu: power-management at ff730000 {
+		u-boot,dm-pre-reloc;
 		compatible = "rockchip,rk3288-pmu", "syscon";
 		reg = <0xff730000 0x100>;
 	};
 
 	sgrf: syscon at ff740000 {
+		u-boot,dm-pre-reloc;
 		compatible = "rockchip,rk3288-sgrf", "syscon";
 		reg = <0xff740000 0x1000>;
 	};
@@ -582,6 +594,7 @@
 		compatible = "rockchip,rk3288-cru";
 		reg = <0xff760000 0x1000>;
 		rockchip,grf = <&grf>;
+		u-boot,dm-pre-reloc;
 		#clock-cells = <1>;
 		#reset-cells = <1>;
 		assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
@@ -600,6 +613,7 @@
 	};
 
 	grf: syscon at ff770000 {
+		u-boot,dm-pre-reloc;
 		compatible = "rockchip,rk3288-grf", "syscon";
 		reg = <0xff770000 0x1000>;
 	};
@@ -804,6 +818,7 @@
 	};
 
 	noc: syscon at ffac0000 {
+		u-boot,dm-pre-reloc;
 		compatible = "rockchip,rk3288-noc", "syscon";
 		reg = <0xffac0000 0x2000>;
 	};
-- 
2.4.3.573.g4eafbef



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