[U-Boot] [PATCH 2/8] Exynos5: Fix rpll_sdiv to support both peach-pit and peach-pi panels

[Simon Glass]

On 3 March 2015 at 07:03, Ajay Kumar <ajaykumar.rs at samsung.com> wrote:
> The existing setting for rpll_sdiv generates 70.5Mhz RPLL
> video clock to drive 1366x768 panel on peach_pit.
>
> This clock rate is not sufficient to drive 1920x1080 panel on peach-pi.
> So, we adjust rpll_sdiv to 3 so that it generates 141Mhz pixel clock
> which can drive peach-pi LCD.
>
> This change doesn't break peach-pit LCD since 141/2=70.5Mhz, i.e FIMD
> divider at IP level will get set to 1(the required divider setting
> will be calculated and set by exynos_fimd_set_clock()) and hence
> peach-pit LCD still works fine.
>
> Signed-off-by: Ajay Kumar <ajaykumar.rs at samsung.com>

Reviewed-by: Simon Glass <sjg at chromium.org>

Tested on Pi.

Tested-by: Simon Glass <sjg at chromium.org>

> ---
>  arch/arm/cpu/armv7/exynos/clock_init_exynos5.c |    4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
> index 0aff3d0..0200fd1 100644
> --- a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
> +++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
> @@ -179,10 +179,10 @@ struct mem_timings mem_timings[] = {
>                 .spll_mdiv = 0xc8,
>                 .spll_pdiv = 0x3,
>                 .spll_sdiv = 0x2,
> -               /* RPLL @70.5Mhz */
> +               /* RPLL @141Mhz */
>                 .rpll_mdiv = 0x5E,
>                 .rpll_pdiv = 0x2,
> -               .rpll_sdiv = 0x4,
> +               .rpll_sdiv = 0x3,
>
>                 .direct_cmd_msr = {
>                         0x00020018, 0x00030000, 0x00010046, 0x00000d70,
> --
> 1.7.9.5
>