[U-Boot] [PATCH 6/8] net: zynq: Fix mdc clock division setting for 100Mbit/s

[Joe Hershberger]

On Tue, Oct 27, 2015 at 10:17 AM, Michal Simek <michal.simek at xilinx.com> wrote:
> Using set and clear macro is incorrect because it is not overwritting
> origin mdc clock division setup.
> For example origin setup is 8(0b001) and new setup is 64(0b100) which
> means 0b101 is setup which is 96 divider.
> Using writel to rewrite all setting like for 1000Mbit/s case.
>
> Signed-off-by: Michal Simek <michal.simek at xilinx.com>

Acked-by: Joe Hershberger <joe.hershberger at ni.com>