[U-Boot] [RFC PATCH v1 1/2] armv8: fsl-layerscape: Reserve memory for PPA

York Sun yorksun at freescale.com
Tue Nov 10 20:17:10 CET 2015 

Primary Protected Application (PPA) is the base of TrustZone for
Freescale Layerscape SoCs. It needs to run in secure memory while
the rest of u-boot can run in non-secure memory. The secure memory
is reserved at the very end of DDR, before debug server and MC
reservations. The address varies depending on the total size of
intalled DDR.

Signed-off-by: York Sun <yorksun at freescale.com>

---

Changes in v1:
  Initial patch.
  Depends on http://patchwork.ozlabs.org/patch/540248/

 README                                            |   14 ++++++++++---
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c           |   23 +++++++++++++++++++++
 arch/arm/include/asm/arch-fsl-layerscape/config.h |    3 +++
 board/freescale/ls2085a/ls2085a.c                 |   17 ---------------
 board/freescale/ls2085aqds/ls2085aqds.c           |   17 ---------------
 board/freescale/ls2085ardb/ls2085ardb.c           |   17 ---------------
 include/configs/ls2085a_common.h                  |    4 ++--
 7 files changed, 39 insertions(+), 56 deletions(-)

diff --git a/README b/README
index ef8d437..e1ca7c2 100644
--- a/README
+++ b/README
@@ -3881,7 +3881,7 @@ Configuration Settings:
 		Scratch address used by the alternate memory test
 		You only need to set this if address zero isn't writeable
 
-- CONFIG_SYS_MEM_TOP_HIDE (PPC only):
+- CONFIG_SYS_MEM_TOP_HIDE:
 		If CONFIG_SYS_MEM_TOP_HIDE is defined in the board config header,
 		this specified memory area will get subtracted from the top
 		(end) of RAM and won't get "touched" at all by U-Boot. By
@@ -5048,6 +5048,10 @@ within that device.
 	normal addressable memory via the LBC. CONFIG_SYS_LS_MC_FW_ADDR is the
 	virtual address in NOR flash.
 
+- CONFIG_SYS_MEM_TOP_HIDE_MIN
+	Define minimum DDR size to be hided from top of the DDR memory.
+	MC requires the region to be aligned with 512MB.
+
 Freescale Layerscape Debug Server Support:
 -------------------------------------------
 The Freescale Layerscape Debug Server Support supports the loading of
@@ -5060,8 +5064,12 @@ This firmware often needs to be loaded during U-Boot booting.
 - CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE
 	Define minimum DDR size required for debug server image
 
-- CONFIG_SYS_MEM_TOP_HIDE_MIN
-	Define minimum DDR size to be hided from top of the DDR memory
+Freescale Layerscape Primary Protected Application (PPA) support
+----------------------------------------------------------------
+Freescale PPA runs in secure DDR, reserved from DDR pool.
+
+- CONFIG_FSL_PPA_RESERVED_DRAM_SIZE
+	If defined, this is reserved in highest address as secure memory
 
 Reproducible builds
 -------------------
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 9d1c70f..690c263 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -537,3 +537,26 @@ void reset_cpu(ulong addr)
 	val |= 0x02;
 	scfg_out32(rstcr, val);
 }
+
+#ifndef CONFIG_FSL_PPA_RESERVED_DRAM_SIZE
+#define CONFIG_FSL_PPA_RESERVED_DRAM_SIZE	0
+#endif
+#ifndef CONFIG_SYS_MEM_TOP_HIDE_MIN
+#define CONFIG_SYS_MEM_TOP_HIDE_MIN	0
+#endif
+unsigned long get_dram_size_to_hide(void)
+{
+	unsigned long dram_to_hide = CONFIG_FSL_PPA_RESERVED_DRAM_SIZE;
+
+/* Carve the Debug Server private DRAM block from the end of DRAM */
+#ifdef CONFIG_FSL_DEBUG_SERVER
+	dram_to_hide += debug_server_get_dram_block_size();
+#endif
+
+/* Carve the MC private DRAM block from the end of DRAM */
+#ifdef CONFIG_FSL_MC_ENET
+	dram_to_hide += mc_get_dram_block_size();
+#endif
+
+	return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN);
+}
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 87bb937..77637a9 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -17,6 +17,9 @@
 #define CONFIG_SYS_FSL_DDR		/* Freescale DDR driver */
 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_5_0
 
+/* High memory for PPA, MC, debug server when applicable */
+#define CONFIG_SYS_MEM_TOP_HIDE		get_dram_size_to_hide()
+
 #if defined(CONFIG_LS2085A)
 #define CONFIG_MAX_CPUS				16
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT		8
diff --git a/board/freescale/ls2085a/ls2085a.c b/board/freescale/ls2085a/ls2085a.c
index 27481e2..6f4c3d4 100644
--- a/board/freescale/ls2085a/ls2085a.c
+++ b/board/freescale/ls2085a/ls2085a.c
@@ -66,23 +66,6 @@ int arch_misc_init(void)
 }
 #endif
 
-unsigned long get_dram_size_to_hide(void)
-{
-	unsigned long dram_to_hide = 0;
-
-/* Carve the Debug Server private DRAM block from the end of DRAM */
-#ifdef CONFIG_FSL_DEBUG_SERVER
-	dram_to_hide += debug_server_get_dram_block_size();
-#endif
-
-/* Carve the MC private DRAM block from the end of DRAM */
-#ifdef CONFIG_FSL_MC_ENET
-	dram_to_hide += mc_get_dram_block_size();
-#endif
-
-	return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN);
-}
-
 int board_eth_init(bd_t *bis)
 {
 	int error = 0;
diff --git a/board/freescale/ls2085aqds/ls2085aqds.c b/board/freescale/ls2085aqds/ls2085aqds.c
index b02d6e8..8898cc3 100644
--- a/board/freescale/ls2085aqds/ls2085aqds.c
+++ b/board/freescale/ls2085aqds/ls2085aqds.c
@@ -251,23 +251,6 @@ int arch_misc_init(void)
 }
 #endif
 
-unsigned long get_dram_size_to_hide(void)
-{
-	unsigned long dram_to_hide = 0;
-
-/* Carve the Debug Server private DRAM block from the end of DRAM */
-#ifdef CONFIG_FSL_DEBUG_SERVER
-	dram_to_hide += debug_server_get_dram_block_size();
-#endif
-
-/* Carve the MC private DRAM block from the end of DRAM */
-#ifdef CONFIG_FSL_MC_ENET
-	dram_to_hide += mc_get_dram_block_size();
-#endif
-
-	return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN);
-}
-
 #ifdef CONFIG_FSL_MC_ENET
 void fdt_fixup_board_enet(void *fdt)
 {
diff --git a/board/freescale/ls2085ardb/ls2085ardb.c b/board/freescale/ls2085ardb/ls2085ardb.c
index 18953b8..efddf74 100644
--- a/board/freescale/ls2085ardb/ls2085ardb.c
+++ b/board/freescale/ls2085ardb/ls2085ardb.c
@@ -217,23 +217,6 @@ int arch_misc_init(void)
 }
 #endif
 
-unsigned long get_dram_size_to_hide(void)
-{
-	unsigned long dram_to_hide = 0;
-
-/* Carve the Debug Server private DRAM block from the end of DRAM */
-#ifdef CONFIG_FSL_DEBUG_SERVER
-	dram_to_hide += debug_server_get_dram_block_size();
-#endif
-
-/* Carve the MC private DRAM block from the end of DRAM */
-#ifdef CONFIG_FSL_MC_ENET
-	dram_to_hide += mc_get_dram_block_size();
-#endif
-
-	return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN);
-}
-
 #ifdef CONFIG_FSL_MC_ENET
 void fdt_fixup_board_enet(void *fdt)
 {
diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h
index 0011e72..1d0d28b 100644
--- a/include/configs/ls2085a_common.h
+++ b/include/configs/ls2085a_common.h
@@ -189,14 +189,14 @@ unsigned long long get_qixis_addr(void);
 /*
  * Carve out a DDR region which will not be used by u-boot/Linux
  *
- * It will be used by MC and Debug Server. The MC region must be
+ * It will be used by PPA, MC and Debug Server. The MC region must be
  * 512MB aligned, so the min size to hide is 512MB.
  */
+#define CONFIG_FSL_PPA_RESERVED_DRAM_SIZE		(2048UL * 1024)
 #if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER)
 #define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE	(256UL * 1024 * 1024)
 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE		(256UL * 1024 * 1024)
 #define CONFIG_SYS_MEM_TOP_HIDE_MIN			(512UL * 1024 * 1024)
-#define CONFIG_SYS_MEM_TOP_HIDE		get_dram_size_to_hide()
 #endif
 
 /* PCIe */
-- 
1.7.9.5

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