[U-Boot] [PATCH] sunxi: Set AHB1 clock to PLL6/3 on all clock_sun6i.h using SoCs

[Ian Campbell]

On Fri, 2015-11-20 at 19:32 +0100, Hans de Goede wrote:
> According to the datasheets the max speed of AHB1 is 276 MHz, so
> setting it to PLL6 / 3 which gives us 200MHz everywhere is fine,
> and gives us a nice speed-up in certain workloads.
> 
> Suggested-by: Chen-Yu Tsai <wens at csie.org>
> Signed-off-by: Hans de Goede <hdegoede at redhat.com>

I suppose you've tested this on at least one such board? In that case:
Acked-by: Ian Campbell <ijc at hellion.org.uk>

> ---
>  arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 4 ----
>  1 file changed, 4 deletions(-)
> 
> diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> index 09337a1..5c76275 100644
> --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> @@ -220,11 +220,7 @@ struct sunxi_ccm_reg {
>  #define CCM_PLL11_CTRL_UPD		(0x1 << 30)
>  #define CCM_PLL11_CTRL_EN		(0x1 << 31)
>  
> -#if defined CONFIG_MACH_SUN8I_H3
>  #define AHB1_ABP1_DIV_DEFAULT		0x00003180 /*
> AHB1=PLL6/3,APB1=AHB1/2 */
> -#else
> -#define AHB1_ABP1_DIV_DEFAULT		0x00002020 /*
> AHB1=AXI/4, APB1=AHB1/2 */
> -#endif
>  
>  #define AXI_GATE_OFFSET_DRAM		0
>