[U-Boot] [PATCH] sunxi: Set AHB1 clock to PLL6/3 on all clock_sun6i.h using SoCs

[Chen-Yu Tsai]

On Sat, Nov 21, 2015 at 11:48 PM, Ian Campbell <ijc+uboot at hellion.org.uk> wrote:
> On Fri, 2015-11-20 at 19:32 +0100, Hans de Goede wrote:
>> According to the datasheets the max speed of AHB1 is 276 MHz, so
>> setting it to PLL6 / 3 which gives us 200MHz everywhere is fine,
>> and gives us a nice speed-up in certain workloads.
>>
>> Suggested-by: Chen-Yu Tsai <wens at csie.org>
>> Signed-off-by: Hans de Goede <hdegoede at redhat.com>
>
> I suppose you've tested this on at least one such board? In that case:
> Acked-by: Ian Campbell <ijc at hellion.org.uk>

I've tested this on some of my boards. It works fine on my Hummingbird A31
and A23 Q8 tablet. However my Sinlinx SinA33 is giving me kernel Oops which
I haven't looked into yet.

ChenYu