[U-Boot] [PATCH] Fix FSL DDR clock adjust calculation.

[Joakim Tjernlund]

T1040 RM specifies CLK_ADJUST as 5 bits starting at bit pos 9
in DDR_DDR_SDRAM_CLK_CNTL, update code to match.

Signed-off-by: Joakim Tjernlund <joakim.tjernlund at transmode.se>
---
 drivers/ddr/fsl/ctrl_regs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 3919257..57077e1 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -1756,7 +1756,7 @@ static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
 	clk_adjust = popts->clk_adjust;
 	ddr->ddr_sdram_clk_cntl = (0
 				   | ((ss_en & 0x1) << 31)
-				   | ((clk_adjust & 0xF) << 23)
+				   | ((clk_adjust & 0x1F) << 22)
 				   );
 	debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
 }
-- 
2.4.6