[U-Boot] [PATCH 1/2] arm: socfpga: mmc: Enable calibration for drvsel and smpsel

[Pavel Machek]

Hi!

> > > > >> How is this SMPLSEL and DRVSEL implemented on Exynos ?
> > > > 
> > > > Exynos is using CLKSEL register in dw-mmc controller.
> > > > It's exynos specific register in dwmmc controller. It's also
> > > > represented 45 degree increment. SELCK_DRV is bit[18:16] or more.
> > > > SELCLK_SAMPLE is bit[2:0] or more. There are other bits relevant to
> > > > tuning clock. '_more_' means that it can be changed bandwidth.
> > > > 
> > > > Anyway, I think there is no right method about finding the best smplclk
> > > > and drvsel. If this is generic method, i will pick this. But i don't
> > > > think so, and there is no benefit for exynos.
> > > > 
> > > > smplclk and drvsel value need to process the tuning sequence.
> > > > There is no tuning case at bootloader, since it's not implemented about
> > > > HS200 or upper mode.
> > > > 
> > > > Clksel an drvsel value are passed by device tree.
> > > 
> > > In that case, maybe SoCFPGA should also pick those values from DT ? It
> > > would keep the code simple and in case there is a problematic board, it
> > > could use u-boot application to perform the tuning.
> > 
> > I prefer not to do that as it narrows the supported use case for the
> > driver.
> 
> How so? It keeps the driver code clean and this code you're adding seems
> like a special-purpose stuff which needs to be done once for particular
> board, no ?

Well... stuff that can be automatically detected is not supposed to be
in the device tree.

clksel and drvsel can be calibrated, so I see some arguments why we
should calibrate them, and not hardcode them in the device tree.
									Pavel
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