[U-Boot] [PATCH v2] spi: tegra20: Add support for mode selection

[Jagan Teki]

On 7 September 2015 at 12:09, Mirza Krak <mirza.krak at hostmobility.com> wrote:
> From: Mirza Krak <mirza.krak at hostmobility.com>
>
> Respect the mode passed in claim_bus call.
>
> Signed-off-by: Mirza Krak <mirza.krak at hostmobility.com>
> ---
>
> Changes in v2:
> * Refactor clearing the CPOL and CPHA bits. Based on comments from Jagan Teki.
>
>  drivers/spi/tegra20_slink.c | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
>
> diff --git a/drivers/spi/tegra20_slink.c b/drivers/spi/tegra20_slink.c
> index fbb665b86f3f..fa39dea2daf1 100644
> --- a/drivers/spi/tegra20_slink.c
> +++ b/drivers/spi/tegra20_slink.c
> @@ -36,6 +36,11 @@ DECLARE_GLOBAL_DATA_PTR;
>  #define SLINK_CMD_ENB                  (1 << 31)
>  #define SLINK_CMD_GO                   (1 << 30)
>  #define SLINK_CMD_M_S                  (1 << 28)
> +#define SLINK_CMD_IDLE_SCLK_DRIVE_LOW          (0 << 24)
> +#define SLINK_CMD_IDLE_SCLK_DRIVE_HIGH         (1 << 24)
> +#define SLINK_CMD_IDLE_SCLK_PULL_LOW           (2 << 24)
> +#define SLINK_CMD_IDLE_SCLK_PULL_HIGH          (3 << 24)
> +#define SLINK_CMD_IDLE_SCLK_MASK                       (3 << 24)
>  #define SLINK_CMD_CK_SDA               (1 << 21)
>  #define SLINK_CMD_CS_POL               (1 << 13)
>  #define SLINK_CMD_CS_VAL               (1 << 12)
> @@ -146,6 +151,7 @@ static int tegra30_spi_claim_bus(struct udevice *dev)
>         struct udevice *bus = dev->parent;
>         struct tegra30_spi_priv *priv = dev_get_priv(bus);
>         struct spi_regs *regs = priv->regs;
> +       unsigned int mode = priv->mode;
>         u32 reg;
>
>         /* Change SPI clock to correct frequency, PLLP_OUT0 source */
> @@ -161,6 +167,17 @@ static int tegra30_spi_claim_bus(struct udevice *dev)
>         /* Set master mode and sw controlled CS */
>         reg = readl(&regs->command);
>         reg |= SLINK_CMD_M_S | SLINK_CMD_CS_SOFT;
> +
> +       /* Set CPOL and CPHA */
> +       reg &= ~(SLINK_CMD_IDLE_SCLK_MASK | SLINK_CMD_CK_SDA);
> +       if (mode & SPI_CPHA)
> +               reg |= SLINK_CMD_CK_SDA;
> +
> +       if (mode & SPI_CPOL)
> +               reg |= SLINK_CMD_IDLE_SCLK_DRIVE_HIGH;
> +       else
> +               reg |= SLINK_CMD_IDLE_SCLK_DRIVE_LOW;
> +

And also this mode should be part of .set_mode ops like speed we have
one more ops to configure mode (clock phase and polarities)

>         writel(reg, &regs->command);
>         debug("%s: COMMAND = %08x\n", __func__, readl(&regs->command));
>
> --
> 2.1.0
>

thanks!
-- 
Jagan | openedev.